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Table of Contents
Basic Building Blocks for Analog Design
Instructions for use
Analog design trade-offs
Analog design methodology
Outline
Outline
Common-Source Stage (CSS)
CSS Simulation - DC
CSS Simulation - DC
CSS Simulation – Small Signal
Diode-connected transistor
Diode-connected transistor
Diode-connected transistor
CSS with diode-connected load
Small signal circuit
CSS with diode-connected load
CSS with Current Source load
CSS with CSL Simulation - DC
CSS-CSL Simulation – Small Sign.
CSS with Triode load
CSS with Source Degeneration
CSS with Source Degeneration
CSS with Source Degeneration
CSS with Source Degeneration
Source Follower (SF)
Source Follower (SF)
Source Follower drawbacks
Common-Gate Stage (CGS)
Common-Gate Stage (CGS)
Cascode Stage (CascS)
Cascode Stage Output Resistance
CascS with current source load
Folded Cascode Stage (FCascS)
Outline
Single-Ended vs Differential
Single-Ended vs Differential
Differential Pair (DP)
Differential Pair
DP – Common mode analysis
DP - Large signal analysis
Differential pair transconductance
DP small signal gain
DP small signal gain
DP Common Mode gain
Common Mode Rejection Ratio
Differential Pair with MOS loads
Cascode Differential Pair
Differential pair mismatch
Outline
Current mirror (CM)
Current mirror simulation
Cascode current mirror (CCM)
Cascode current mirror (CCM)
Cascode current mirror simulation
Low Voltage CCM (LVCCM)
Low Voltage CCM simulation (1)
Low Voltage CCM simulation (2)
Current mirrors: comparison
Current mirror output impedance
Current mirror mismatch
Outline
Differential Pair + Active CM
Differential Pair + Active CM
Differential Pair + Active CM
Noise in a DP + Active CM
Noise in a DP + Active CM
Offset of a DP + Active CM
List of Acronyms
Outline
Op-amp application examples
Single-stage Op Amp
Two-stage Op Amp
Two-stage Op Amp
Two-stage Op Amp