ICTP Microprocessor Laboratory Second Central American Regional Course on Advanced VLSI Design Techniques Benemérita Universidad Autónoma de Puebla, Puebla, Mexico 29 November – 17 December 2004 Basic Building Blocks for Analog Design Puebla, December 2004 Giovanni Anelli CERN - European Organization for Nuclear Research Physics Department Microelectronics Group CH-1211 Geneva 23 – Switzerland Giovanni.Anelli@cern.ch Instructions for use This lecture deals with the basis of analog design. I have decided to prepare the material in a rater “formal” way, deriving almost all the necessary formulas. This was done to try to give you some complete and precise material for future reference. We will not need to assimilate all the formulas today. The important thing is that we recognize in each formula which are the important parameters and trends. Puebla, December 2004 Giovanni Anelli, CERN Analog design trade-offs NOISE POWER DISSIPATION LINEARITY GAIN ANALOG DESIGN OCTAGON INPUT/OUTPUT IMPEDANCE SUPPLY VOLTAGE VOLTAGE SWINGS SPEED Behzad Razavi, “CMOS Technology Characterization for Analog and RF Design", IEEE JSSC, vol. 34, no. 3, March 1999, p. 268. Puebla, December 2004 Giovanni Anelli, CERN Analog design methodology Define specifications Extract schematic from layout Choose architecture Layout Versus Schematic (LVS) check Simulate schematic Extracted schematic simulations Simulate schematic varying T, VDD, process parameters BLOCK DONE! Masks layout In a complex design, this will be repeated for every block of the design hierarchy. Design Rules Check (DRC) Puebla, December 2004 Giovanni Anelli, CERN Outline • • • • • Single-stage amplifiers The differential pair The current mirror Differential pair + active current mirror Operational amplifier (op amp) design B. Razavi, Design of Analog CMOS Integrated Circuits, McGraw-Hill International Edition, 2001. P.R. Gray, P.J. Hurst, S.H. Lewis, R.G. Meyer, Analysis and Design of Analog Integrated Circuits, J. Wiley & Sons, 4th edition, 2001. R. Gregorian, Introduction to CMOS Op-Amps and Comparators, J. Wiley & Sons, 1999. R.L. Geiger, P.E. Allen and N.R. Strader, VLSI Design Techniques for Analog and Digital Circuits, McGraw-Hill International Edition, 1990. D.A. Johns and K. Martin, Analog Integrated Circuit Design, J. Wiley & Sons, 1997. Puebla, December 2004 Giovanni Anelli, CERN Outline • Single-stage amplifiers Common-source Stage Common-drain Stage (Source Follower) Common-gate Stage Cascode Stage Folded cascode Stage • • • • The differential pair The current mirror Differential pair + active current mirror Operational amplifier (op amp) design Puebla, December 2004 Giovanni Anelli, CERN Common-Source Stage (CSS) VDD Vout = VDD − R D DC characteristic RD Vout Vin Small signal gain G = Small signal gain (with channel length modulation) β ( Vin − VT )2 2n ∂Vout β = −R D ( Vin − VT ) = −gmR D ∂Vin n G = −gm (r0 // R D ) = −gm r0R D r0 + R D Small signal model in saturation G Vin D + gmVGS S Puebla, December 2004 Vout RD ro Giovanni Anelli, CERN The above results could also have been obtained directly from the small signal model CSS Simulation - DC 2.5E-02 3 2.5 1.5E-02 1.5 1.0E-02 1 Vout Ids gm 0.5 5.0E-03 0 0.0E+00 0 0.5 1 1.5 2 Vin [ V ] Puebla, December 2004 Giovanni Anelli, CERN 2.5 IDS [ A ], g m [ S ] 2.0E-02 2 Vout [ V ] W = 100 µm L = 0.5 µm R = 100 Ω The maximum small signal gain is only –1.8!!! CSS Simulation - DC Increasing the value of the load resistor to 1 kΩ we have 3 1.2E-02 Vout Ids gm 1.0E-02 2 8.0E-03 1.5 6.0E-03 1 4.0E-03 0.5 2.0E-03 0 0.0E+00 0 0.5 1 1.5 2 Vin [ V ] Puebla, December 2004 Giovanni Anelli, CERN 2.5 IDS [ A ], g m [ S ] Vout [ V ] 2.5 W = 100 µm L = 0.5 µm R = 1000 Ω The maximum small signal gain is now –9.6. 0.905 1.774 0.903 1.772 1.77 0.901 1.768 0.899 1.766 0.897 1.764 0.895 1.762 0 2 4 6 8 R = 1000 Ω Ids [ mA ] Vin [ V ] CSS Simulation – Small Signal 10 0.905 0.738 0.903 0.736 0.734 0.901 0.732 0.899 0.73 0.897 0.728 0.895 0.726 0 2 4 6 8 We inject at the input a sinusoid with frequency 1 kHz, peak to peak amplitude 1 mV AND dc offset = 0.9 V. The DC offset is important to be in the right bias point. V out [ V ] Vin [ V ] t [ ms ] gm = 9.6 mS The input voltage is converted in a current by the transistor and then in a voltage again by the resistor. 10 t [ ms ] Puebla, December 2004 Giovanni Anelli, CERN Diode-connected transistor A MOS transistor behaves as a small signal resistor when gate and drain are shorted. A transistor in this configuration is referred to as “diode-connected” transistor. The device is always in saturation. To calculate the impedance of this device we use the small-signal equivalent circuit and a test voltage generator (in red). The ratio between the voltage vx applied and the current ix gives the impedance. ix G, D gmVGS ro vx ix = gm v x + + S R= vx r0 vx 1 1 = ≈ 1 gm ix gm + r0 The calculation show that the impedance is given by the parallel of two resistors, 1/gm and r0. Puebla, December 2004 Giovanni Anelli, CERN Diode-connected transistor Impedance seen looking into the source. VDD G, D ro gmVGS ix vx S + ix vx v ix = gm v x + x + gmb v x r0 R= gmbVBS B + vx 1 1 = ≈ 1 gm + gmb ix gm + gmb + r0 In this case we have three resistances in parallel: 1/gm, 1/gmb and r0. Puebla, December 2004 Giovanni Anelli, CERN Diode-connected transistor Impedance seen looking into the drain with a resistor RS between the source and ground. G, D ix vx ix + ro gmVGS gmbVBS S RS ix = gm (v x − ixR S ) + vx B RS v x − i xR S − gmbixR S r0 ⎛ 1⎞ 1 + ⎜⎜ gm + gmb + ⎟⎟ ⋅ R S r0 ⎠ v 1 gm + gmb ⎝ R= x = ≈ + ⋅ RS 1 ix g g m m gm + r0 Without bulk effect (gmb) and the channel length modulation (r0) we would see the series of 1/gm and RS. If RS = 0 we find again 1/gm. Puebla, December 2004 + Giovanni Anelli, CERN CSS with diode-connected load VDD Small signal gain T2 G = −gm1 ⋅ Vout Vin T1 G = −gm1 ⋅ R out = −gm1 ⋅ (R D1 // R S2 ) 1 gm2 + gmb2 + 1 1 + r02 r01 ≈− gm1 gm2 1 g ⋅ = − ⋅ m1 gm2 gm2 + gmb 2 n2 gm2 For T1 and T2 in strong inversion G = − 1 ⋅ n2 (W / L )1 (W / L )2 The equations above can be obtained in three different ways: • Using the results found for single transistors (as we have done) • Starting from the DC equations and doing some mathematics (boring…) • Using the small signal equivalent circuit (see next slide) In an N-well CMOS process, the bulk contacts of all the NMOS are connected together to ground (substrate). On the other hand, each bulk contact of the PMOS (each well) can be connected to a desired signal. Puebla, December 2004 Giovanni Anelli, CERN Small signal circuit G2, D2 i = gm1vin + ro2 gm2VGS2 gmb2VBS2 v out r01 i = −gm2 v out − v out − gmb 2 v out r02 S2, Vout i G1 Vin D1 + r01 gm1VGS1 S1 B1 B2 ⎛ 1 1⎞ ⎟⎟ gm1vin = − v out ⎜⎜ gm2 + gmb 2 + + r01 r02 ⎠ ⎝ G= v out = −gm1 ⋅ vin g m2 Puebla, December 2004 Giovanni Anelli, CERN 1 + gmb 2 1 1 + + r02 r01 CSS with diode-connected load Substituting the NMOS load with a PMOS load, we get rid of the bulk effect. VDD Small signal gain G = −gm1 ⋅ T2 Vout Vin In strong inversion, we have T1 gm2 1 g ≈ − m1 1 1 gm2 + + r02 r01 G=− µ n (W / L )1 µ p (W / L )2 Drawbacks of this configuration: • It is difficult to have high gain • Vout_max = VDD – ⏐VGS2⏐. • To have gain, (W/L)2 is made smaller than (W/L)1. This will limit the maximum output voltage, since ⏐VGS2⏐will be quite higher than VT2. Puebla, December 2004 Giovanni Anelli, CERN CSS with Current Source load To increase the gain, we can use the output resistance of a transistor. T2 provides the DC current bias to T1, and has a high output impedance. The bias current is determined by Vb. VDD Vb r01 ⋅ r02 1 Small signal G = −g (r // r ) = −g ⋅ g = − ⋅ m1 01 02 m1 m1 1 1 r01 + r02 gain + r02 T2 Vout Vin T1 r01 This solution gives a much higher gain than the other solutions and has a better DC output swing, since Vout_max = VDD – ⏐VDS2_sat⏐ and Vout_min = VDS1_sat. The output of the circuit shown is in an undefined state (highimpedance node). This circuit needs therefore an “external system” to fix its output DC bias point (we need a feedback network!). Puebla, December 2004 Giovanni Anelli, CERN CSS with CSL Simulation - DC CSS-CSL = Common Source Stage with Current Source Load W1 = 100 µm L1 = 0.5 µm Load Transistor 3 1.2E-04 1.4E-03 2.5 1.0E-04 1.2E-03 2 8.0E-05 1 gm [ S ] 6.0E-05 1.5 W2 = 800 µm L2 = 4 µm 1.0E-03 IDS [ A ] V out [ V ] Input Transistor 8.0E-04 6.0E-04 4.0E-05 4.0E-04 Vout 0.5 2.0E-05 Ids 0 0.0E+00 0 0.5 1 1.5 2 2.0E-04 0.0E+00 2.5 0 Vin [ V ] Puebla, December 2004 0.5 1 Vin [ V ] Giovanni Anelli, CERN 1.5 2 2.5 CSS-CSL Simulation – Small Sign. Small signal simulations 0.64 101 Vin [ V ] 100.8 0.636 100.7 0.634 100.6 0.632 100.5 0.63 100.4 0 2 4 6 8 Ids [ µA ] 100.9 0.638 0.638 1.5 1.4 0.636 1.3 0.634 1.2 0.632 1.1 0.63 1 0 2 4 6 8 10 V out [ V ] Vin [ V ] 1.6 The DC offset is important to be in the right bias point (especially for the output!) With a current of just 100 µA and the same input transistor dimensions as in the case of the CSS with load resistor, we have a gain of –373. 10 t [ ms ] 0.64 We inject at the input a sinusoid with frequency 1 kHz, peak to peak amplitude 1 mV and DC offset = 0.635 V. N.B. The output current is smaller than what it should be. The bias point is so critical that the simulator has some problems… t [ ms ] Puebla, December 2004 Giovanni Anelli, CERN CSS with Triode load This circuit is the same as the CSS with Current Source load, but the gate bias of transistor T2 is low enough to make sure that T2 works in the linear region and therefore it behaves as a resistor. VDD Small signal gain Vb T2 Vout Vin G = −gm1 ⋅ T1 1 µ PCox W2 (VDD − Vb − VTP ) L2 To have T2 in the linear region, we must have Vb < Vout – VTP (where VTP is a positive number). If we can not take Vb < 0 V, we can take it = 0 V. In this case we must have Vout > VTP. The principal drawback of this circuit is that the small-signal gain depends on many parameters. Puebla, December 2004 Giovanni Anelli, CERN CSS with Source Degeneration VDD RD Vout Vin RS In some applications, the square-law dependence of the drain current upon the gate overdrive voltage introduces excessive non linearity. RS “smoothes” this effect since it takes a portion of the gate overdrive voltage. At the limit, for RS >> 1/gm, the small signal gain does not depend on gm (and therefore on IDS) anymore. It is interesting to note that the approximated small signal gain (which can be easily calculated with the small signal equivalent circuit) can also be calculated as if RS and 1/gm were two resistors in series. Small signal gain (approximation) Puebla, December 2004 gm G=− =− ⋅ RD 1 1 + gmR S + RS gm Giovanni Anelli, CERN RD CSS with Source Degeneration The approximated small signal voltage gain can also be seen as the product of the small signal equivalent transconductance of the degenerated CS Stage multiplied by the total resistance seen at the output (RD). To calculate the exact small signal voltage gain we need the exact small signal equivalent transconductance and the output resistance of the degenerated CS Stage. Both these quantities can be calculated with the equivalent small signal circuits. VDD RD Small signal gain (approximation) G=− gm ⋅ R D = −gm _ eq ⋅ R D 1 + gmR S Vout Vin RS Exact small signal gmr0 equivalent gm _ eq = R S + r0 + (gm + gmb ) ⋅ R S ⋅ r0 transconductance (with channel length DO IT YOURSELF modulation and bulk effect) AS AN EXERCISE! Puebla, December 2004 Giovanni Anelli, CERN CSS with Source Degeneration Calculation of the output resistance of the degenerated CS Stage. G ix Vin vx D ix + gmbVBS S RS B ix = −gm v s + R out _ CSS _ deg Puebla, December 2004 ro gmVGS vx − vs − gmb v s r0 RS v s = i xR S vx = = r0 + R S + (gm + gmb ) ⋅ r0R S ix Giovanni Anelli, CERN vx + CSS with Source Degeneration Exact small signal gain of the degenerated CS Stage. VDD Approximated small signal gain Gappr . = − gm ⋅ R D = −gm _ eq ⋅ R D 1 + gmR S RD Vout Vin Output resistance of the degenerated CS Stage R out = R out _ CSS _ Deg // R D R out _ CSS _ deg = r0 + R S + (gm + gmb ) ⋅ r0R S RS Exact small signal gain gm _ eq = G = −gm _ eq ⋅ R out gmr0 R S + r0 + (gm + gmb ) ⋅ R S ⋅ r0 Exercise: try to obtain the same equation with the complete small signal circuit Puebla, December 2004 Giovanni Anelli, CERN Source Follower (SF) The analysis of the Common Source Stage (CSS) with current source load demonstrated that to have a high voltage gain we have to have a high load impedance. If we want to use a CSS to drive a low impedance load, we have to put a “buffer” between the CSS and the load. The simplest buffer is the Source Follower (also called Common Drain Stage). VDD How do we obtain the small signal gain? We could use the small signal equivalent circuit or we can be clever and reuse what we have seen up to now! Vin Vout RS G= G= ⎛ ⎞ Vout 1 ⎟⎟ = gm ⋅ ⎜⎜ R S // Vin gm + gmb + 1/ r0 ⎠ ⎝ gm gm + gmb + 1 1 + r0 R S = gm ⋅ R S 1 + (gm + gmb ) ⋅ R S The gain of our buffer is never one! It is, in the best case, 1/n Puebla, December 2004 Giovanni Anelli, CERN Source Follower (SF) The Source Follower with a resistor is highly non linear, since the drain current in T1 is a strong function of the input DC level. We can therefore replace the resistor with a current source. ⎞ ⎛ 1 gm1 ⎟⎟ = GSF _ NMOS = gm1 ⋅ ⎜⎜ r02 // gm1 + gmb1 + 1/ r01 ⎠ gm1 + gmb1 + 1/ r01 + 1/ r02 ⎝ VDD Vin T1 Vout Vb T2 The gain is in this case close to 1/n (still not 1…). The circuit is still non linear due to the body effect (non linear dependence of VT1 upon the source potential). This can be solved using a PMOS Source Follower, in which both the transistors have the body (well) connected to the source. In this case, we have: ⎞ ⎛ 1 gm1 ⎟⎟ = GSF _ PMOS = gm1 ⋅ ⎜⎜ r02 // gm1 + 1/ r01 ⎠ gm1 + 1/ r01 + 1/ r02 ⎝ The gain can be in this case very close to one! Puebla, December 2004 Giovanni Anelli, CERN Source Follower drawbacks ⎞ ⎛ 1 gm1 ⎟⎟ = G = gm1 ⋅ ⎜⎜ R L // r02 // gm1 + 1/ r01 ⎠ gm1 + 1/ r01 + 1/ r02 + 1/ R L ⎝ VDD Vb G≈ T2 Vout Vin RL T1 Puebla, December 2004 gm1 RL = gm1 + 1/ R L R L + 1/ gm If the source follower has to drive a low impedance, we risk to have a gain which is significantly smaller than one. Another important drawback is that source followers shift the signal by one VGS. This is a drawbacks especially in low voltage circuit, where this causes a limitation in the voltage headroom. On the other hand, if the power supply voltage is high enough, source followers can be used as voltage level shifters. Giovanni Anelli, CERN Common-Gate Stage (CGS) In Common-Source Stages and Source Followers the input signal is applied to the gate. We can also apply it to the source, obtaining what is called a Common-Gate Stage (CGS) VDD R out = R out _ CGS // R D RD Vout Vb R in = 1 + R D / r0 R D + r0 = gm + gmb + r0 1 + (gm + gmb ) ⋅ r0 G= Vin R out _ CGS = r0 G= R out R in _ R D =0 EXERCISE! = (r0 // R D ) ⋅ (gm + gmb + 1/ r0 ) r ⋅ (gm + gmb ) + 1 RD = RD ⋅ 0 ≈ gm ⋅ n ⋅ R D R in R D + r0 The input impedance of a CGS is relatively low, but this only if the load impedance in low. The gain is slightly higher to the one of a CSS, since we apply the signal to the source. N.B. We have calculated the small signal gain using 2 different methods (red and blue). The results are identical! Puebla, December 2004 Giovanni Anelli, CERN Common-Gate Stage (CGS) With the results obtained, it is now very easy to study the most “general” case, which includes the impedance RS of the signal source, the channel modulation effect and the bulk effect. Let’s call Rin the resistance seen by the ideal voltage source. R D + r0 R in = R S + 1 + (gm + gmb ) ⋅ r0 VDD RD Vout Vb RS vin ⋅ R D = v out R in v out R D 1 + (gm + gmb ) ⋅ r0 G= = = RD ⋅ vin R in R S ⋅ [1 + (gm + gmb ) ⋅ r0 ] + R D + r0 This result is very similar to the one of a Common Source Stage with source degeneration. The gain here is still slightly higher due to the body effect. It is now also easy to calculate the resistance seen into the output. R out = R D // R out _ CSS _ deg + Vin Puebla, December 2004 R out _ CSS _ deg = r0 + R S + (gm + gmb ) ⋅ r0R S Giovanni Anelli, CERN Cascode Stage (CascS) The “cascade” of a Common-Source Stage (V-I converter) and of a Common-Gate Stage is called a “Cascode”. VDD v out RD r01 = − vin ⋅ gm1 ⋅ ⋅ RD R D + r02 r01 + 1 + (gm2 + gmb 2 ) ⋅ r02 REMINDER I Vout Vb Vin T2 T1 R1 G = −gm1 ⋅ r01 ⋅ R D ≈ −gm1R D R D + r02 r01 + 1 + (gm2 + gmb 2 ) ⋅ r02 I1 = The gain is practically the same as in the case of a Common-Source Stage. Puebla, December 2004 Giovanni Anelli, CERN R2 ⋅I R1 + R 2 R2 Cascode Stage Output Resistance One nice property of the cascode stage can be discovered looking at the resistance seen in the drain of T2. This is quickly done if we look at T2 as a Common-Source Stage with a degeneration resistor = r01. Rout R out _ CSS _ deg = r0 + R S + (gm + gmb ) ⋅ r0R S Vb Vin T2 R out _ CascS = r01 + r02 + (gm2 + gmb2 ) ⋅ r01r02 ≈ (gm2 + gmb2 ) ⋅ r01r02 T1 Compared to a CSS, the output impedance is “boosted” by a factor (gm2 + gmb2) r02. The disadvantage of the cascode configuration is that the minimum output voltage is now the sum of the saturation voltages of T1 and T2. It must therefore be used with care in low voltage circuits. Puebla, December 2004 Giovanni Anelli, CERN CascS with current source load To fully profit of the high output impedance of the cascode stage, it seems natural to load it with a high impedance load, like a current source. R out _ CascS = r01 + r02 + (gm2 + gmb2 ) ⋅ r01r02 VDD Vb1 R out = R out _ CascS // r03 T3 Vout Vb2 Vin G ≈ −gm1R out T2 T1 If r03 is not high enough, we can use the cascode principle to boost the output impedance of the current source as well. N.B. Remember that the DC output level here is not well defined, and that we will need a feedback loop. Puebla, December 2004 Giovanni Anelli, CERN Folded Cascode Stage (FCascS) VDD Vin VDD RD T1 Ib Vout T2 Vb Vin T1 Vb T2 Vout Ib RD This solution is has a lower output impedance than the standard CascS and consumes more current for the same performance. Puebla, December 2004 Giovanni Anelli, CERN Outline • Single-stage amplifiers • The differential pair Differential signal advantages The differential pair – – – – Common Mode Analysis Large Signal Analysis Small Signal Analysis Common Mode Rejection Ratio (CMMR) Differential pair with MOS loads Differential Pair Mismatch • The current mirror • Differential pair + active current mirror • Operational amplifier (op amp) design Puebla, December 2004 Giovanni Anelli, CERN Single-Ended vs Differential A single-ended signal is defined as a signal measured with respect to a fixed potential (usually, ground). A differential signal is defined as a signal measured between two nodes which have equal and opposite signal excursions. The “center” level in differential signals is called the Common-Mode (CM) level. The most important advantage of differential signals over single-ended signals is the much higher immunity to “environmental” noise. As an example, let’s suppose to have a disturbance on the power supply. VDD VDD RD Vout_SE Puebla, December 2004 RD Vout + Giovanni Anelli, CERN RD Vout - Single-Ended vs Differential The Common-Mode disturbances disappear in the differential output. Vdd Vout_SE = Vout + Vout Vout_diff Vout _ diff = Vout + − Vout − Puebla, December 2004 Giovanni Anelli, CERN Differential Pair (DP) VDD Vin1 RD Vin,CM RD Vout1 Vin2 Vout2 Vout2 Vin1 Vin2 ISS Vout,CM Vout1 t The current source has a very important function, since it makes the sum of the currents in the two ISS = − ⋅ v V R branches (I1 + I2= ISS) independent from the input out ,CM DD D 2 common mode voltage. The output common mode voltage is then given by: Puebla, December 2004 Giovanni Anelli, CERN Differential Pair VDD VDD RD Vout1 RD Vout1 Vout2 Vout2 Vin1 VDD - RD ISS Vin1 - Vin2 Vin2 Vout1 - Vout2 RD ISS ISS N.B. The small signal gain is the slope of this plot Puebla, December 2004 Giovanni Anelli, CERN Vin1 - Vin2 - RD ISS DP – Common mode analysis To better understand what can be the maximum voltage excursion of the input, we substitute the ideal current source with a real one. VDD vin,CM _ min = VGS1 + ( VGS3 − VT 3 ) = VGS1 + VDS _ SAT 3 RD RD Vout1 Vin1 vin,CM _ max Vout2 T1 Vb T2 T3 Vin2 ISS ⎞ ⎛ = min ⎜ VDD − R D + VT 1 , VDD ⎟ 2 ⎠ ⎝ And what can be the maximum excursion of the output? v out _ min = VDS _ SAT1 + VDS _ SAT 3 v out _ max = VDD Puebla, December 2004 Giovanni Anelli, CERN DP - Large signal analysis With the basic transistor equations, some patience and some mathematics we can obtain the equation for the plot shown. Vout1 - Vout2 vlim = RD ISS 2ISS β /n vin1 − vin2 = ∆Vin ID1 − ID2 = ∆I Vlim Vin1 - Vin2 - Vlim ∆v out = − R D ⋅ ∆I - RD ISS ∆I = − ISS For ∆Vin < − vlim For − vlim < ∆Vin < vlim 4ISS β 2 ∆I = ∆Vin − ∆Vin 2n β /n ∆I = ISS For ∆Vin > vlim Puebla, December 2004 v out1 − v out 2 = ∆Vout Giovanni Anelli, CERN Differential pair transconductance Deriving the current difference as a function of the input voltage difference we obtain the transconductance Gm of the differential pair. ∆I Gm ISS - Vlim Vlim ∆Vin 4ISS 2 − 2∆Vin β β /n ∂∆ I = Gm = ∂∆Vin 2n 4ISS 2 − ∆Vin β /n Puebla, December 2004 ∆Vin Vlim - Vlim ∆vin = 0 Giovanni Anelli, CERN Gm = 2β ISS n 2 DP small signal gain From the transconductance Gm of the differential pair when the differential stage is balanced (∆vin = 0), we obtain the small signal gain G. Gm = 2β ISS n 2 ∆v out = − R D ⋅ ∆I = − R D ⋅ Gm ⋅ ∆vin ∆v out 2β ISS = − RD ⋅ G= ∆vin n 2 The term circled in red looks suspiciously familiar to us… It is the transconductance in strong inversion of a transistor carrying a current ISS/2 ! So we can write G = − R D ⋅ gm Puebla, December 2004 Giovanni Anelli, CERN DP small signal gain Now that we know it, is is quite obvious to recognize it looking again at the circuit schematic. VDD RD RD Vout1 Vin1 Vout2 T1 Vb T2 P Vin2 We can see the circuit as two common source stages with degenerated resistor, and superimpose the effects. Or, even better, we can realize that the point P is (ideally) AC grounded. v out1 = −gm ⋅ R D ⋅ vin1 v out 2 = −gm ⋅ R D ⋅ vin2 T3 v out1 − v out 2 = −gm ⋅ R D ⋅ (vin1 − vin2 ) Puebla, December 2004 Giovanni Anelli, CERN DP Common Mode gain We have seen that ideally in a differential pair the output voltage does not depend on the common mode input voltage. But in fact the non infinite output impedance r03 of the current source has an influence, since the point P do not behave as an AC ground anymore. The symmetry in this circuit suggests that we can see it as two identical half circuits in parallel. This makes the analysis much easier. VDD VDD RD RD Vout1 Vin1 RD Vout2 T1 Vb Puebla, December 2004 T2 P What do we have here? A CSS with source degeneration. Easy… Vin2 Vout Vin,CM T1 GCM = 2r03 T3 Giovanni Anelli, CERN v out RD =− vin,CM 1/ gm + 2r0 Common Mode Rejection Ratio The variation of the common mode output voltage with the common mode input voltage is generally small and not so worrying. MUCH MORE concerning is when we have a differential output as a consequence of a common mode variation at the input! This can happen if the circuit is not fully symmetric (mismatch!). Let's call GCM-DM the gain of this common-mode to differential-mode conversion. A difference in the transconductances of the two transistors, for example, would give: ∆gm ⋅ R D GCM−DM = (gm1 + gm2 ) r03 + 1 We see that it is essential to have a good current source (very high r03). To make possible a meaningful comparison between different differential circuit, we want to compare the undesirable differential output given by a common mode input variation and the wanted differential output given by a differential input. We define the Common Mode Rejection Ratio (CMRR) as: CMRR = Taking into account ONLY the g transconductance mismatch, we obtain CMRR ≈ m (1 + 2gmr03 ) ∆gm Puebla, December 2004 Giovanni Anelli, CERN G GCM−DM Differential Pair with MOS loads To analyze the two circuits we can now make use of the half-circuit concept and profit from all the results obtained up to now. ⎛ 1 ⎞ g G = − gmN ⎜⎜ // r0N // r0P ⎟⎟ ≈ − mN gmP ⎝ gmP ⎠ G = − gmN (r0N // r0P ) VDD T3 VDD T4 T1 T2 Vin2 Vin1 ISS Puebla, December 2004 T3 T4 T1 T2 ISS Giovanni Anelli, CERN Vb Vout2 Vout1 Vout2 Vout1 Vin1 Vb Vin2 Cascode Differential Pair And, of course, the gain can be boosted using common-gate stages. VDD Vb3 T7 T8 Vb3 Vb2 T5 T6 Vb2 Vout1 Vb1 Vin1 T3 T4 T1 T2 G ≈ − gm1 (gm3r03r01 // gm5r05r07 ) Vout2 Cascode stages were used a lot in the past, when the supply voltages were relatively high (few volts). Vin2 In deep submicron technologies they are used with more care. Vb1 ISS Puebla, December 2004 Giovanni Anelli, CERN Differential pair mismatch The two transistors have the same drain current σ ∆VGS = σ 2 ∆Vth ⎛ I ⎞ ⎜ +⎜ σ ∆β / β ⎟⎟ ⎝ gm ⎠ 2 22 σ ∆VGS [mV ] 20 18 16 14 σ ∆β /β = 1 . 4 % σ ∆VT = 4.5 mV 12 10 8 2I σ ∆VT 6 4 2 0 1.E-02 1.E-01 1.E+00 1.E+01 I.C. Puebla, December 2004 Giovanni Anelli, CERN 1.E+02 1.E+03 Outline • Single-stage amplifiers • The differential pair • The current mirror Standard Current Mirror Cascode Current Mirror Low-voltage Cascode Current Mirror Current Mirror Output Impedance Current Mirror Mismatch • Differential pair + active current mirror • Operational amplifier (op amp) design Puebla, December 2004 Giovanni Anelli, CERN Current mirror (CM) We suppose that all the transistors have the same µ, Cox and VT. λ is the same if the transistors have the same L VDD IREF WR LR I1 I2 W1 L1 W2 L2 W1 (1 + λ 1VDS1 ) L I1 = IREF ⋅ 1 WR (1 + λ R VDSR ) LR GND To have an exact replica of the reference current, we have to make the transistor identical AND they must have the same VDS. When this is not possible, choosing long devices reduces the effect of λ. Precise current ratios can be obtained playing with the ratio between the transistor widths (not the lengths!). Puebla, December 2004 Giovanni Anelli, CERN Current mirror simulation 0.25 µm technology, VDD = 2.5 V, IREF = 100 µA, WR = W1 = 100 µm, LR = L1 0.12 @ VDS1 = 2.5 V 0.1 I1 [ mA ] 0.08 VDS1 _ min_ SI = 0.06 2I1 µCoxn( W1 / L1 ) VDS1 _ min_ WI = 4nφ t 0.04 L = 10 um L = 0.5 um 0.02 0 0 0.5 1 1.5 2 2.5 VDS1 [ V ] Puebla, December 2004 Giovanni Anelli, CERN T1 L = 0.5 [µm] L = 10 [µm] ID [µA] 106 100.3 β [mA/V2] 60.54 2.488 gm [mS] 1.77 0.594 VT [mV] 635.7 635.6 VGS [mV] 636.7 943 VDS_sat [mV] 70.76 269.7 Rout [MΩ] 0.866 14.5 Cascode current mirror (CCM) VG3 must be fixed so that VD1 = VD2. I3 VDD IREF VD3 W3 L3 VG3 VD1 VD2 W1 L1 W2 L2 GND Making L1 = L2 and therefore having λ1 = λ2, we obtain that the current I3 practically does not depend on the voltage VD3. Of course, all the devices must be in saturation (the circuit is not suitable for low voltage applications). I3 = IREF ⋅ ∆VD2 ≈ (gm3 W2 / L 2 W1 / L1 ∆VP + gmb 3 ) ⋅ r03 Important: L3 can be different from L1 and L2. How do we fix VG3 so that VD1 = VD2 ? Puebla, December 2004 Giovanni Anelli, CERN Cascode current mirror (CCM) VDD Transistor 4 does the job here! Transistors 1 & 2 decide the current ratio. IREF I3 Transistors 3 & 4 fix the bias VD1 = VD2. VD3 W4 L4 W3 L3 VD1 VD2 W1 L1 W2 L2 GND These results are valid even if transistors 3 & 4 suffer from body effect. I3 = IREF ⋅ W2 / L 2 W1 / L1 W2 / L 2 W3 / L 3 = W1 / L1 W4 / L 4 The problem of this current mirror is that VD3 > VDS3 + VGS2. Puebla, December 2004 Giovanni Anelli, CERN Cascode current mirror simulation 0.25 µm technology, VDD = 2.5 V, IREF = 100 µA 0.12 @ VD3 = 2.5 V T2 T3 ID [µA] 100 100 0.08 β [mA/V2] 60.54 13.08 0.06 gm [mS] 1.676 1.211 VT [mV] 635.7 852 VGS [mV] 636.7 962.4 VDS_sat [mV] 70.75 128.7 Rout [MΩ] 0.108 1.037 I3 [ mA ] 0.1 0.04 W1 = W2 = 100 µm L1 = L2 = 0.5 µm W3 = W4 = 50 µm L3 = L4 = 1 µm 0.02 0 0 0.5 1 1.5 2 2.5 VD3 [ V ] Puebla, December 2004 Giovanni Anelli, CERN Low Voltage CCM (LVCCM) VDD IREF I3 VD3 W4 VB L4 VD1 W3 L3 VD2 W1 L1 GND W2 L2 The main difference of this current mirror compared to the standard cascode current mirror is that here we can lower the voltages VD1 and VD2 to the limit of the saturation of transistors T1 and T2. I3 = IREF ⋅ W2 / L 2 W1 / L1 W2 / L 2 W3 / L 3 = W1 / L1 W4 / L 4 The minimum output voltage (VD3) here is just two saturation voltages. Puebla, December 2004 Giovanni Anelli, CERN Low Voltage CCM simulation (1) 0.25 µm technology, VDD = 2.5 V, IREF = 100 µA @ VD3 = 2.5 V 0.12 T2 T3 ID [µA] 100 100 0.08 β [mA/V2] 60.5 13.57 0.06 gm [mS] 1.641 1.208 VT [mV] 635.7 692.4 VGS [mV] 642.5 798.3 VDS_sat [mV] 72.87 123.6 Rout [MΩ] 0.021 1.6 I3 [ mA ] 0.1 W1 = W2 = 100 µm L1 = L2 = 0.5 µm W3 = W4 = 50 µm L3 = L4 = 1 µm 0.04 0.02 0 0 0.5 1 1.5 2 2.5 VD3 [ V ] Puebla, December 2004 Giovanni Anelli, CERN Low Voltage CCM simulation (2) 0.12 VDD 0.1 IREF I3 [ mA ] 0.08 I3 VD3 0.06 This plot shows that we can lower the voltage VB until it reaches the limit VGS3 + VDS2_sat 0.04 0.02 W4 VB L4 VD1 VD2 W1 L1 0 0.4 0.6 0.8 1 1.2 1.4 VB [ V ] Puebla, December 2004 Giovanni Anelli, CERN W3 L3 GND W2 L2 Current mirrors: comparison 0.12 IOUT [ mA ] 0.1 Vout_min Precision CM VDS1_sat Poor (unless large L) CCM VGS2 + VDS3_sat Good LVCCM VDS2_sat + VDS3_sat Good 0.08 0.06 0.04 CM - L = 1 um 0.02 LVCCM CCM 0 0 0.5 1 1.5 2 VOUT [ V ] Puebla, December 2004 Giovanni Anelli, CERN 2.5 Current mirror output impedance CCM Standard CM VDD VDD LVCCM Vout WR LR W1 L1 GND rout = r01 Puebla, December 2004 Iout Iout Vout Iout Vout IREF IREF IREF VDD W4 L4 W3 L3 W1 L1 W2 L2 GND W4 L4 Vb W1 L1 GND rout = r02 + r03 + (gm3 + gmb3 ) ⋅ r02r03 Giovanni Anelli, CERN W3 L3 W2 L2 Current mirror mismatch The two transistors have the same gate voltage σ ∆I/I = σ σ ∆I/I [%] 2 ∆β / β ⎛ gm ⎞ +⎜ σ ∆Vth ⎟ ⎝ I ⎠ 14 σ ∆β /β = 1 . 4 % 12 σ ∆VT = 4.5 mV 10 I 2 8 6 4 σ ∆β / β 2 0 1.E-02 1.E-01 1.E+00 I.C. Puebla, December 2004 Giovanni Anelli, CERN 1.E+01 1.E+02 1.E+03 Outline • • • • Single-stage amplifiers The differential pair The current mirror Differential pair + active current mirror Common mode, small signal and large signal analysis Noise Offset • Operational amplifier (op amp) design Puebla, December 2004 Giovanni Anelli, CERN Differential Pair + Active CM Current mirrors can also process a signal, and they can therefore be used as active elements. A differential pair with an active current mirror is also called a differential pair with active load. The current mirror here has also the important role to make a differential to single-end conversion! VDD Common Mode Analysis T3 T4 vin,CM _ min = VGS1 + VDS _ SAT 5 Vout T2 T1 Vin vin,CM _ max = min (VDD − VGS 3 + VT 1 , VDD ) Maximum output excursion v out _ min = VDS _ SAT 2 + VDS _ SAT 5 Vb Puebla, December 2004 T5 v out _ max = VDD − VDS _ SAT 4 Giovanni Anelli, CERN Differential Pair + Active CM Let’s now calculate the small-signal behavior, neglecting the bulk effect for simplicity. The circuit is NOT symmetric, and therefore we can not use the halfcircuit principle here. As a first approximation, we can consider the common sources of the input transistors as a virtual ground. The small-signal gain G can be seen as the product of the total transconductance of the stage and of the output resistance. G = Gm ⋅ R out VDD v v iout = −gm1 in − gm2 in = −gm1,2 ⋅ vin T3 T4 2 2 iout iout V G = = −gm1,2 out + m vin 2 T1 T2 − vin 2 R out = r02 // r04 G = −gm1,2 (r02 // r04 ) ISS Puebla, December 2004 vin Giovanni Anelli, CERN Differential Pair + Active CM In reality, the current source is not ideal, and this has an effect on the gain we have just calculated. This effect is in general negligible. What is not negligible is the effect of r05 on the common mode gain. For a common mode input signal the circuit can be seen symmetric! It can be shown that even for a perfectly symmetric circuit (no mismatch) a CM signal at the input (∆vin,CM) generates an unwanted signal at the output (∆vout). VDD T3 Common Mode Gain (neglecting bulk effect and r01,2) T4 Vout Vin,CM T2 T1 Vb Puebla, December 2004 T5 GCM ∆Vout = ∆Vin,CM r03 ,4 1 // 2gm3,4 2 =− = 1 + r05 2gm1,2 gm1,2 1 =− 1 + 2gm1,2r05 gm3,4 Giovanni Anelli, CERN Noise in a DP + Active CM VDD VDD 2I 2I vin2 vin2 v 2tot i2out 2 vload 2 vload v 2tot Puebla, December 2004 2 ⎞ 2 ⎛ g m _ load 2 ⎟ ⋅ vload = 2 ⋅ v in + 2 ⋅ ⎜ 2 ⎟ ⎜ g m _ in ⎠ ⎝ Giovanni Anelli, CERN i2out Noise in a DP + Active CM VDD v 2 tot _ 1 / f K a _ load ⋅ µ load ⋅ L2in ⎞ 1 ⎛⎜ ⎟ ⋅ ∆f = 2⋅ 2 ⋅ ⋅ 1+ 2 ⎜ Cox WinLin f ⎝ K a _ in ⋅ µ in ⋅ Lload ⎟⎠ K a _ in 2I v 2 tot Make WinLin big and Lload > Lin v 2tot _ th ⎛ ⎛W⎞ ⎜ µ load ⎜ ⎟ 2 ⎜ ⎝ L ⎠ load = 4kTn γ ⋅ ⋅ ⎜1+ ⎛W⎞ Win ⎜ µ ⎟ 2µ inCox I ⎜ in ⎜ L ⎝ ⎠ in Lin ⎝ ⎛W⎞ ⎛W⎞ Make ⎜ ⎟ > ⎜ ⎟ ⎝ L ⎠ in ⎝ L ⎠ load Puebla, December 2004 Giovanni Anelli, CERN ⎞ ⎟ ⎟ ⎟ ⋅ ∆f ⎟ ⎟ ⎠ Offset of a DP + Active CM RANDOM OFFSET (WORST CASE) VDD v off = ∆VT 1,2 + 2I I gm1,2 ⎛ ∆β1,2 ∆β 3 ,4 gm3 ,4 ⎞ ⎜ ⎟ + + ∆ V T 3,4 ⎟ ⎜ β β 3,4 I ⎝ 1,2 ⎠ SYSTEMATIC OFFSET v off Vin T1 T2 Vout T3 The difference in the drain voltages of T1 and T2 gives origin a difference in the DC currents in the two branches. T4 “COMMON MODE” OFFSET As we have already seen, a common mode signal at the input gives a non zero output voltage signal. Puebla, December 2004 Giovanni Anelli, CERN List of Acronyms • CSS: Common-Source Stage • CSS-CSL: Common-Source Stage with Current Source Load • SF: Source Follower (also called Common-Drain Stage) • CGS: Common-Gate Stage • CascS: Cascode Stage = CSS + CGS • FCascS: Folded Cascode Stage • DP: Differential Pair • CM: Current Mirror • CCM: Cascode Current Mirror • LVCCM: Low-Voltage Cascode Current Mirror • CMRR: Common Mode Rejection Ratio Puebla, December 2004 Giovanni Anelli, CERN sorry… ☺ Outline • • • • • • Single-stage amplifiers The differential pair The current mirror Differential pair + active current mirror Frequency analysis of an amplifier Operational amplifier (op amp) design Single-stage op amps Two-stage op amps Puebla, December 2004 Giovanni Anelli, CERN Op-amp application examples NONINVERTING CONFIGURATION INVERTING CONFIGURATION R2 Vin Vout Vin Vout R1 R1 R2 BUFFER Vin Vout = Vin R2 G=− R1 R G = 1+ 2 R1 G=1 The above equations are valid only if the gain of the op-amp is very high! Puebla, December 2004 Giovanni Anelli, CERN Single-stage Op Amp VDD T7 Vb2 T8 T5 T6 Vb2 Vout Vb1 T3 T4 T1 T2 Vin Vb1 Several different solutions can be adopted to make a Single-stage amplifier. If high gains are needed, we can use, for example, cascode structures. With single-stage amplifiers it is difficult to obtain at the same time high gain and voltage excursion, especially when other characteristics are also required, such as speed and/or precision. Two-stage configurations in this sense are better, since they decouple the gain and voltage swing requirements. ISS Puebla, December 2004 Giovanni Anelli, CERN Two-stage Op Amp G = gm1,2 (r01,2 // r03 ,4 ) ⋅ gm5 ,6 (r05 ,6 // r07 ,8 ) The second stage is very often a CSS, since this allows the maximum voltage swing. VDD T3 T4 T5 Vb1 T1 T6 The output voltage swing in this case is VDD - |2VDS_SAT| T2 Vin Vout1 Vout2 ISS Vb2 T7 Puebla, December 2004 T8 Giovanni Anelli, CERN Two-stage Op Amp G = { gm1,2 [(gm3 , 4 + gmb 3 , 4 )r03 , 4r01,2 )] // [(gm5 ,6 + gmb 5 ,6 )r05 ,6r07 ,8 )] }⋅ gm9 ,10 (r09 ,10 // r011,12 ) VDD Vb3 T7 T8 Vb3 Vb2 T5 T6 Vb2 To increase the gain, we can again make use, in the first stage, of cascode structures. T9 T10 Vb1 Vout1 T3 T4 T1 T2 Vb1 Vout2 Vin Vb4 T11 Puebla, December 2004 ISS T12 Giovanni Anelli, CERN Vb4 Two-stage Op Amp G = gm1,2 (r01,2 // r03 , 4 ) ⋅ gm6 (r06 // r08 ) Two-stage op amps can also have a single-ended output. In this case, we kept the differential behavior of the first stage, and is the current mirror T7-T8 which does the differential-to-single ended conversion. VDD T3 T4 T5 Vb T1 T6 T2 Vin Vout ISS T7 Puebla, December 2004 T8 Giovanni Anelli, CERN