Revised November 1999

74AC20
Dual 4-Input NAND Gate
General Description

Features
■ ICC reduced by 50%

The AC20 contains four 4-input NAND gates.

■ Outputs source/sink 24 mA

Ordering Code:
Order Number

Package Number

Package Description

M14A

14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow Body

M14D

14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

74AC20SC
74AC20SJ
74AC20MTC
74AC20PC

MTC14
N14A

14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide

Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.

Logic Symbol

Connection Diagram
IEEE/IEC

Pin Descriptions
Pin Names

Description

An, Bn, Cn, Dn

Inputs

On

Outputs

FACT is a trademark of Fairchild Semiconductor Corporation.

© 1999 Fairchild Semiconductor Corporation

DS009918

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74AC20 Dual 4-Input NAND Gate

November 1988

74AC20

Absolute Maximum Ratings(Note 1)
Supply Voltage (VCC)

Recommended Operating
Conditions

−0.5V to +7.0V

DC Input Diode Current (IIK)
VI = −0.5V

−20 mA

VI = VCC + 0.5V

+20 mA

DC Input Voltage (VI)

Supply Voltage (VCC)

0V to VCC

Output Voltage (VO)

−0.5V to VCC + 0.5V

0V to VCC
−40°C to +85°C

Operating Temperature (TA)

DC Output Diode Current (IOK)

Minimum Input Edge Rate (∆V/∆t)

VO = −0.5V

−20 mA

VO = VCC + 0.5V

125 mV/ns

VIN from 30% to 70% of VCC

+20 mA

DC Output Voltage (VO)

2.0V to 6.0V

Input Voltage (VI)

VCC @ 3.3V, 4.5V, 5.5V

−0.5V to VCC + 0.5V

DC Output Source
± 50 mA

or Sink Current (IO)
DC VCC or Ground Current

± 50 mA

per Output Pin (ICC or IGND)
Storage Temperature (TSTG)

Note 1: Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power
supply, temperature, and output/input loading variables. Fairchild does not
recommend operation of FACT circuits outside databook specifications.

−65°C to +150°C

Junction Temperature (TJ)
PDIP

140°C

DC Electrical Characteristics
Symbol

Parameter

TA = +25°C

VCC
(V)

VIH

VIL

VOH

Typ

TA = −40°C to +85°C

Units

Conditions

Guaranteed Limits

Minimum HIGH Level

3.0

1.5

2.1

2.1

Input Voltage

4.5

2.25

3.15

3.15

5.5

2.75

3.85

3.85

Maximum LOW Level

3.0

1.5

0.9

0.9

Input Voltage

4.5

2.25

1.35

1.35

5.5

2.75

1.65

1.65

Minimum HIGH Level

3.0

2.99

2.9

2.9

Output Voltage

4.5

4.49

4.4

4.4

5.5

5.49

5.4

5.4

3.0

2.56

2.46

4.5

3.86

3.76

5.5

4.86

4.76

VOUT = 0.1V
V

or VCC − 0.1V
VOUT = 0.1V

V

or VCC − 0.1V

V

IOUT = −50 µA
VIN = VIL or VIH

VOL

IOH = −12 mA
V

IOH = −24 mA
IOH = −24 mA (Note 2)

Maximum LOW Level

3.0

0.002

0.1

0.1

Output Voltage

4.5

0.001

0.1

0.1

5.5

0.001

0.1

0.1

3.0

0.36

0.44

4.5

0.36

0.44

5.5

0.36

0.44

5.5

± 0.1

± 1.0

µA

V

IOUT = 50 µA
VIN = VIL or VIH
IOL = 12 mA

V

IOL = 24 mA
IOL = 24 mA (Note 2)

IIN

Maximum Input

(Note 4)

Leakage Current

IOLD

Minimum Dynamic

5.5

75

mA

VOLD = 1.65V Max

IOHD

Output Current (Note 3)

5.5

−75

mA

VOHD = 3.85V Min

ICC

Maximum Quiescent

5.5

20.0

µA

VIN = VCC

(Note 4)

Supply Current

2.0

or GND

Note 2: All outputs loaded; thresholds on input associated with output under test.
Note 3: Maximum test duration 2.0 ms, one output loaded at a time.
Note 4: IIN and ICC @ 3.0V are guaranteed to be less than or equal to the respective limit @ 5.5V VCC.

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VI = VCC, GND

2

Symbol
tPLH

Parameter
Propagation Delay
Propagation Delay

tPHL

VCC

TA = +25°C

(V)

CL = 50 pF

TA = −40°C to +85°C
CL = 50 pF

(Note 5)

Min

Typ

Max

Min

Max

3.3

2.0

6.0

8.5

1.5

10.0

5.0

1.5

5.0

7.0

1.0

8.0

3.3

1.5

5.0

7.0

1.0

9.0

5.0

1.5

4.0

6.0

1.0

7.0

Units

ns
ns

Note 5: Voltage Range 3.3 is 3.3V ± 0.3V
Voltage Range 5.0 is 5.0V ± 0.5V

Capacitance
Typ

Units

CIN

Symbol

Input Capacitance

Parameter

4.5

pF

VCC = OPEN

CPD

Power Dissipation Capacitance

40.0

pF

VCC = 5.0V

3

Conditions

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74AC20

AC Electrical Characteristics

74AC20

Physical Dimensions inches (millimeters) unless otherwise noted

14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow Body
Package Number M14A

www.fairchildsemi.com

4

74AC20

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M14D

5

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74AC20

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package Number MTC14

www.fairchildsemi.com

6

74AC20 Dual 4-Input NAND Gate

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Package Number N14A

Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
2. A critical component in any component of a life support
device or system whose failure to perform can be reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.

1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the
user.

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7

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