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Table of Contents
Revision History
Table of Contents
List of Figures
List of Tables
About This Document
Purpose and Audience
Acronyms and Abbreviations
Document Conventions
Section 1: Introduction
Section 2: Architecture Overview
Section 3: Quad Processor
Quad Processor Architecture
Core Pipeline Operation
Processor Registers
ALUs
Signaling Bits
Load Immediate
Small Immediates
Branches
Horizontal Vector Rotation
Pack and Unpack
Thread Control
Inter-Processor Synchronisation
Register-Mapped Input/Output
Varyings
Uniforms
Texture and Memory Units
Special Functions Unit
Vertex Pipeline Memory
Tile Buffer
Inter-Processor Mutex
Host Interrupt
Processor Stalls
QPU Instruction Encoding
ALU Instructions
Condition Codes
ALU Input Muxes
Signaling Bits
Small Immediate
Pack/Unpack Bits
Load Immediate Instructions
Semaphore Instruction
Branch Instruction
QPU Instruction Set
Op Add
Op Mul
Summary of Instruction Restrictions
QPU Register Address Map
Section 4: Texture and Memory Lookup Unit
QPU Interface
Texture Data Storage
Texture and Memory Lookup Unit Setup
Texture Data Types
Texture Filter Types
Texture Modes
Normal 2D Texture Mode
Cube Map Mode
Interface Registers
Section 5: Tile Buffer
QPU Interface
Scoreboard
Color Read and Write
Z and Stencil
Coverage Read
Tile Buffer Access Restrictions
QPU Registers for Tile Buffer Access
Section 6: FEP-to-QPU Interface
Initial Data
Varyings Interpolation
Section 7: VPM and VCD
QPU Reading and Writing of VPM
QPU Control of VCD and VDW
QPU Registers for VPM and VCD Functions
VPM Vertex Data Formats
Vertex Attribute Format in VPM from VCD
Shaded Vertex Format in VPM for PSE
Shaded Coordinates Format in VPM for PTB
Section 8: System Control
System Operation
System Pipelines and Modes
Section 9: Control Lists
Control Record IDs and Data Summary
Primitive List Formats
VG Coordinate Array Primitives (ID=41)
VG Inline Primitives (ID=42)
Compressed Primitive List (ID=48)
Clipped Primitive (with Compressed Primitive List) (ID=49)
Shader State Record Formats
Shaded Vertex Format in Memory
Section 10: V3D Registers
V3D Register Address Map
V3D Register Definitions
Control List Executor Registers (Per Thread)
V3D Pipeline Registers
QPU Scheduler Registers
VPM Registers
Cache Control Registers
QPU Interrupt Control
Pipeline Interrupt Control
V3D Miscellaneous Registers
V3D Identity Registers
Performance Counters
Error and Diagnostic Registers
Section 11: Texture Memory Formats
Micro-tiles
Texture Format (T-format)
Linear-tile Format (LT-Format)
Appendix A: Errata List
Appendix B: Base Addresses