a FEATURES Two Matched ADCs on Single Chip CMOS Compatible I/O Low Power (400 mW) Dissipation Single +5 V Supply On-Chip Voltage Reference Self-Biased for AC Coupled Inputs 28-Pin SOIC Package APPLICATIONS Direct Broadcast Satellite (DBS) Receivers QAM Demodulators Wireless LANs VSAT Receivers Dual 6-Bit, 60 MSPS Monolithic A/D Converter AD9066 FUNCTIONAL BLOCK DIAGRAM +VS VT 6-BIT ADC D0A-D5A INA REF A ENCODE 6-BIT ADC D0B-D5B INB REF B VB PRODUCT DESCRIPTION The AD9066 is a dual 6-bit ADC that has been optimized for low cost in-phase and quadrature (I&Q) demodulators. Primary applications include digital direct broadcast satellite applications where broadband quadrature phase shift keying (QPSK) modulation is used. In these receivers the recovered signal is separated into I&Q vector components and digitized. To reduce total system cost and power dissipation, the AD9066 provides an internal voltage reference and operates from a single +5 volt power supply. Digital outputs are CMOS compatible and rated to 60 MSPS conversion rates. The digital input (ENCODE) utilizes a CMOS input stage with a TTL compatible (1.4 V) threshold. The AD9066 is housed in a 28-pin SOIC package and available in two temperature grades. The AD9066JR is rated for operation over the 0°C to +70°C commercial temperature range. The AD9066AR is rated for the –40°C to +85°C industrial temperature range. The internal voltage reference insures that the analog input is biased to midscale with low offset when driven from an ac coupled source. In dc coupled applications, the midscale voltage reference can be used to control external biasing amplifiers to minimize offsets due to variations in temperature or supply voltage. PIN CONFIGURATION ENCODE 1 28 D5A (MSB) +VS 2 27 D4A GND 3 26 D3A GND 4 25 D2A +VS 5 24 D1A INA 6 GND 7 +VS 8 VT 9 REF A 10 23 D0A (LSB) AD9066 TOP VIEW (Not to Scale) 22 GND 21 +VS 20 D5B (MSB) 19 D4B INB 11 18 D3B REF B 12 17 D2B VB 13 16 D1B NC 14 15 D0B (LSB) NC = NO CONNECT REV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. © Analog Devices, Inc., 1995 One Technology Way, P.O. Box 9106, Norwood. MA 02062-9106, U.S.A. Tel: 617/329-4700 Fax: 617/326-8703 AD9066–SPECIFICATIONS ELECTRICAL CHARACTERISTICS (+V S = +5 V, AIN = 15.5 MHz, Encode Rate = 60 MSPS, TC = TA) Parameter Test Level Temp Min ANALOG INPUT Full-Scale Input Range Gain Matching (FS Range) DC Input (Midscale)1 Input Offset1 Input Capacitance Input Resistance (DC) Input Bandwidth (3 dB) Gain Flatness (to 15 MHz) Integral Linearity Differential Linearity Monotonicity VI IV V VI IV VI V V VI VI VI Full Full +25°C Full Full Full +25°C +25°C Full Full Full 475 SWITCHING PERFORMANCE Max Conversion Rate Output Delay (tV)2 Output Delay (tPD)2 Aperture Uncertainty (Jitter) Aperture Time (tA) VI IV IV V V Full Full Full +25°C +25°C 60 4 DYNAMIC PERFORMANCE3 Effective Number of Bits SINAD Harmonic Distortion (THD) Crosstalk Rejection VI VI VI IV +25°C +25°C +25°C +25°C 5.3 34 40 40 ENCODE INPUT Logic High Voltage Logic Low Voltage Input High Current Input Low Current Pulse Width High Pulse Width Low VI VI VI VI IV IV Full Full Full Full Full Full 2.0 DIGITAL OUTPUTS Output Coding Logic High Voltage (IOH = 1 mA) Logic Low Voltage (IOL = 1 mA) VI VI Full Full Full POWER SUPPLY +VS Supply Voltage Power Supply Rejection Ratio1 +VS Supply Current Power Dissipation4 VI IV VI VI Full Full Full Full AD9066JR Typ 500 Max Min 525 16 450 +1.0 15 50 –1.0 22 +1.0 +0.5 –1.0 –0.5 +VS – 1.1 –1.0 25 10 40 100 0.25 –1.0 –0.5 AD9066AR Typ 500 Max Units 530 16 mV mV V LSBs pF kΩ MHz dB LSBs LSBs +VS – 1.1 Guaranteed 10 40 100 0.25 +1.0 15 52 +1.0 +0.5 Guaranteed 60 4 10 1.0 MSPS ns ns ps rms ns 5.7 36 50 50 Bits dB dB dBc 11 12 10 1.0 5.7 36 50 50 5.3 34 40 40 2.0 0.8 500 500 7.0 7.0 0.8 500 500 7.0 7.0 Offset Binary Offset Binary 3.8 3.8 0.4 4.75 110 80 400 V V µA µA ns ns 5.25 130 120 600 4.75 110 80 400 0.4 V V 5.25 130 120 600 V mV/V mA mW NOTES 1 For ac coupled applications, the ADC is internally biased to insure that the midpoint transition of the ADC is within the limits specified with no signal applied. For dc coupled applications, the dc value of the midpoint transition voltage will track the supply voltage within the limits shown for dc input (midscale) plus the dc offset. Power Supply Rejection Ratio (PSRR) refers to the variation of the input signal range (gain) to supply voltage. 2 tV and tPD are measured from the 1.4 V level of the Clock and the 50% level between VOH and VOL. The ac load on all the digital outputs during test is 10 pF (max), the dc load will not exceed ± 40 µA. 3 Effective number of bits (ENOB) and THD are measured using a FFT with a pure sine wave analog input @ 15.5 MHz, 1 dB below full scale. ENOB is calculated by ENOB = (SNR – 1.76 dB)/6.02; THD is measured from full scale to the sum of the second through seventh harmonic of the input. 4 Typical thermal impedance for the “R” style (SOIC) 28-pin package is: θJC = 4°C/W, θCA = 41°C/W, θJA = 45°C/W. Specifications subject to change without notice. –2– REV. 0 AD9066 PIN DESCRIPTIONS ABSOLUTE MAXIMUM RATINGS Pin Min Max Units Pin No. Name ENCODE +VS INA, INB VT REF A, REF B VB D0–D5 Current OUT –0.5 +VS 7.0 +VS +VS +VS +VS 20 V V V V V V mA 1 –0.5 2.5 –0.5 0.0 2 3 4 5 6 7 8 9 EXPLANATION OF TEST LEVELS Test Level Description I II 100% Production Tested 100% Production Tested at +25°C, and Sample Tested at Specified Temperatures Sample Tested Only Parameter Is Guaranteed by Design Parameter Is Typical Value Only 100% Tested at +25°C for AD9066JR 100% Tested Over Full Temperature Range for AD9066AR III IV V VI 10 11 12 13 14 15 DIE LAYOUT AND MECHANICAL INFORMATION 16 17 18 19 20 21 22 23 24 25 26 27 28 D2A D3A D4A D5A ENCODE +VS GND GND Die Dimensions . . . . . . . . . . . . . . . . . 132 × 68 × 21 (± 1) mils Pad Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 × 4 mils Metalization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Aluminum Backing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . None Substrate Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ground Transistor Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5,810 Passivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . Silicon Nitride Die Attach . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Silver Filled Bond Wire . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Gold D/A +VS INA D0A GND GND +VS +VS VT D5B Function ENCODE TTL Compatible CMOS Clock, Samples on Rising Edge. +VS +5 V Supply for Digital Input. GND Ground. GND Ground. +5 V Supply (Analog). +VS INA Channel A Analog Input. GND Ground. +VS +5 V Supply (Analog). VT Top of Voltage Reference, Bypass to GND. REF A Mid Reference to ADC A, Bypass to GND. INB Channel B Analog Input. REF B Mid Reference to ADC B, Bypass to GND. VB Bottom of Reference Ladder, Bypass to GND. NC No Connect. D0B (LSB) Digital Outputs Channel B, CMOS Compatible. D1B D2B D3B D4B D5B (MSB) +5 V Supply for Digital Outputs. +VS GND Ground. D0A (LSB) Digital Outputs Channel A, CMOS Compatible. D1A D2A D3A D4A D5A (MSB) ORDERING GUIDE D4B D3B D2B D1B D0B NC VB INB REF B REF A Model Temperature Range Package Option* AD9066AR AD9066JR AD9066/PCB –40°C to +85°C 0°C to +70°C 0°C to +70°C R-28 R-28 Evaluation Board *R = “SO” Small Outline Package. CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD9066 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. REV. 0 –3– WARNING! ESD SENSITIVE DEVICE AD9066 The easiest way to increase the input range will be to force VB to a lower voltage. Using an external amplifier, the voltage at VB may be forced as low as 3.0 V (3.58 nominal). Using the previously described relationship for full scale and the internal resistor ladder values, 3.0 V at VB will result in a nominal fullscale input range of 705 mV. 5.8 ENCODE = 60 MSPS 5.7 ENOB – Bits 5.6 5.5 A larger input range can be established by taking the VT voltage all the way to the supply voltage level while pulling VB to 3.0 V. This would force a 2 V potential across the ladder and create a full-scale input range of 1.6 V. 5.4 5.3 Greater flexibility and improved power supply rejection can be achieved by forcing external voltage references at both the top and bottom of the resistor ladder. 5.2 1 10 MHz 100 111111 Figure 1. ENOB vs. Analog Input Frequency 2n–2 = 62 5.8 ANALOG INPUT = 10.1 MHz 100000 5.7 011111 ENOB – Bits 5.6 5.5 000001 5.4 000000 5.3 – FULL SCALE MIDSCALE + FULL SCALE 5.2 100 10 Figure 3. MHz Figure 2. ENOB vs. Encode Rate +VS = 5V 400 USING THE AD9066 Analog Input and Voltage References VT The AD9066 is optimized to allow ac coupled inputs with a fullscale input range of 500 mV ± 5%. An LSB weight is approximately 8 mV. The full-scale input range is defined as the voltage range that accommodates 2n – 2 codes of equally weighted LSBs (between the first and last code transitions). For the AD9066 there are 32 codes above and below the midscale voltage of the A see Figure 3). 310 VS 310 40k 40k REFA REF B 310 INPUT 310 VB 2mA 1.4V THRESHOLD The full-scale input range of the AD9066 is equal to 500/ 620 × (VT – VB), or nominally 500 mV. For dc coupled applications, the REF A and REF B voltages can be used to feed back offset compensation signals. This will allow the midscale transition voltage of the ADCs to track supply and temperature variations. a. Reference Circuit b. Encode Input VS VS OUTPUTS In the event that offset correction signals are generated digitally, the REF pins would not be required. Figure 4a shows the equivalent circuit for the internal references. All component tolerances are ± 25%. 40k REF Gain Variation The full-scale input range is established by the current through the two matched resistor ladders (620 ohms each nominal). Therefore the gain of the ADC may be modified by forcing different voltages across the top and bottom voltage taps (VT and VB). c. Output Bits d. Analog Input Figure 4. Equivalent Circuits –4– REV. 0 AD9066 Timing ENCODE 866Ω The duty cycle of the encode clock for the AD9066 is critical in obtaining rated performance of the ADC. Rated maximum and minimum pulse widths should be maintained, especially for sample rates greater than 40 MSPS. 6 BITS 866Ω INA 1/2 AD812 The AD9066 provides latched data outputs with two pipeline delays. The length and load on the output data lines should be minimized to reduce power supply transients inside the AD9066 which might diminish dynamic performance. 2kΩ 866Ω N tA N+1 ENCODE –15V tV VALID DATA FOR N – 3 tPD VALID DATA FOR N – 2 VALID DATA FOR N – 1 6 BITS +15V 866Ω N+2 D0–D5 REF A OR REF B 1/2 AD712 866Ω ANALOG INPUT AD9066 1/2 AD712 2kΩ 866Ω INB 1/2 AD812 Figure 6. Bipolar Input Using AD812 Drive for AD9066 Layout should follow high frequency/high speed design guidelines. In addition the capacitance around the inverting input to the AD812 should be minimized through a tight layout and the use of low capacitance chip resistors for gain setting. DATA CHANGING Figure 5. Timing Diagram The data is invalid during the period between tV and tPD. This period refers to the time required for the AD9066 to fully switch between valid CMOS logic levels. When latching the output data, be careful to observe latch setup and hold time restrictions as well as this data invalid period when designing the system timing. Quadrature Receiver Using the AD9066 Although any type of input signal may be applied, the AD9066 has been optimized for low cost in-phase and quadrature (I&Q) demodulators. Primary applications include digital direct broadcast satellite applications where broadband quadrature phase shift keying (QPSK) modulation is used. In these receivers the recovered signal is separated into I&Q vector components and digitized. Layout and Signal Care To insure optimum performance, a single low impedance ground plane is recommended. Analog and digital grounds should be connected together at the AD9066. Analog and digital power supplies should be bypassed, at the device, to ground through 0.1 µF ceramic capacitors. AD9066 IF IN An evaluation board (order ADI Part # AD9066/PCB) is available to aid designers and provide a suggested layout. The use of sockets may limit the dynamic performance of the part and is not recommended except for prototype or evaluation purposes. LPF ADC LPF ADC 90° VCO VCO Driving the AD9066 with a Bipolar Input The analog input range of the AD9066 is between 3.7 V and 4.2 V. Because the input is offset, the normal method of driving the analog input is to use a blocking capacitor between the analog source and the AD9066 analog input pins. In applications where DC coupling must be employed, the simple circuit shown in Figure 6 will take a bipolar input and offset it to the operating range of the AD9066. Figure 7. Simplified Block Diagram For data symbol rates less than 10 Mbaud, the AD607 IF/RF receiver subsystem provides an ideal solution for the second conversion stage of a complete receiver system. Figure 8 shows the AD9066 and AD607 used together. The AD607 accepts inputs as high as 500 MHz which may be the output of the first IF stage or RF signals directly. The IF/ RF signal is mixed with the local oscillator to provide an IF frequency of 400 kHz to 22 MHz. This signal is filtered externally and then amplified with an on-chip AGC before being synchronously demodulated with an on-chip PLL carrier recovery circuit. The outputs are digitized with the AD9066. The digital outputs may be processed with a DSP chip such as the ADSP2171, ADSP-21062, general purpose DSP or ASIC. To offset the input, the midpoint voltage of the AD9066 is buffered off chip and then inverted with an AD712, a low input bias current dual op amp. This inverted midpoint is then fed to a summation amplifier that combines the bipolar input with the inverted offset voltage. The summation amplifier is an AD812, a wideband current feedback amplifier that provides good bandwidth and low distortion. REV. 0 –5– AD9066 CLOCK LOCAL OSCILLATOR 1 CLKIN –16dBM 28 27 26 6 10Ω VMID VINA 330Ω 330Ω OPTIONAL BPF OR LPF 23 AD9066 PLL 20 100nF 90° 10Ω 4.7µF A OUTPUTS (INPHASE) 24 0° BANDPASS FILTER RF INPUT (ANTENNA) 25 19 11 100nF VINB 18 17 B OUTPUTS (QUADRATURE) 16 15 MIDPOINT BIAS GENERATOR AGC DETECTOR AGC VOLTAGE AD607 BIAS CIRCUIT PTAT VOLTAGE RECEIVED SIGNAL STRENGTH INDICATOR Figure 8. Digitizer with AD607 Receiver Circuit Inputs to the evaluation board are +5 V (AVCC and DVCC), AIN A, AIN B and ENC. The outputs from the board are RECONSTRUCT OUTPUT A, RECONSTRUCT OUTPUT B and digital output J105. Theory of Operation The AD9066 dual ADC employs a patented interpolated flash architecture. This architecture enables 64 possible quantization levels with only 32 comparator preamplifiers. This keeps input capacitance to a minimum. The midpoint of the reference ladder is fed back to the analog input, allowing easy biasing of the ADC to midscale for ac coupled applications. Power supplies are connected through banana jacks AVCC, DVCC, AGND and BGND. With your system power off, connect the power supply ground to both AGND and BGND. Then connect the +5 V lead to AVCC and DVCC. AVCC may be tied to DVCC or powered separately. AGND and BGND are tied to a common plane. This board requires 240 mA total from the +5 V supply. Switching supplies are not recommended because high frequency emissions from the switching circuitry will cause unwanted spectral disruption and seriously degrade performance. As shown in Figure 5a, a simple resistor is used to provide the reference ladder midpoint to the analog input. The high impedance MOS inputs of the comparators insure no static voltage drop across the resistor. This eliminates the need for an active buffer (and its inherent offsets) to set the reference midpoint at the analog input. The outputs of the comparators are converted to a 6-bit word and converted to CMOS levels. The digital signals are latched at six stages (two pipeline delays) in the signal path. The digital outputs are CMOS with approximately equal rise and fall times. The analog input should be connected to SMB connectors AIN A and AIN B. The analog inputs may be tied together or driven from independent sources. Because the analog input range is centered about 3.9 V, the analog input is ac coupled from the connector to the input pin of the device and terminated into 50 ohms. If the analog input is offset properly, these capacitors (C30 and C40) may be jumpered across. The encode clock utilizes a CMOS input stage with TTL compatible (1.4 V) thresholds. Internal clock buffers minimize external clock drive requirements. The TTL or CMOS encode source should be connected to the SMB labeled ENC. If desired, a socket for a TTL/CMOS clock oscillator is provided. To use this option, R100 should be removed from the circuit. For optimal performance, a clean, jitter free encode source should be used. Although the AD9066 is not a high resolution converter, it is capable of digitizing higher frequency analog inputs which are subject to the effects of jitter. CONVERTER EVALUATION BOARD The AD9066 evaluation board (see Figure 9) is designed to provide optimal performance for evaluation of the AD9066 analog-to-digital converter. This board encompasses all of our experiences in high speed layout and testing. This ensures that you will attain the highest level of performance in device evaluations. Data out of the AD9066 is buffered using two 74AS574s, one per output side. The output data is connected to the high speed digital data interface. This data may be connected to a capture memory for spectral analysis or connection into the target system. Analog reconstruct is provided for each converter for users without the ability to perform spectral analysis or for reference. This output provides a 1 volt peak-to-peak signal. The board is a four layer PCB consisting of two signal layers, one ground and one +5 V layer. The signal layers are on the top and bottom for easy access. The inner ground layer is solid and common to both analog and digital circuitry. The power layer is split to isolate the AD9066 from the potentially noisy digital interface. The AD9066 is connected to the banana jack labeled AVCC while the digital circuitry is connected to DVCC. These two can be tied together externally by the customer for single supply setups. –6– REV. 0 AD9066 REFHI REFLO RMIDA C101 0.1µF +5V RMIDB C103 0.1µF C102 0.1µF C107 0.1µF E3 E1 E2 +5V U100 14 VCC OUT A05 U108 17 ADV7128R 8 VEE 7 K1115 ENCODE U101 AD9066R SMBPN J100 AVCC DGND GND AVCC VINA R100 49.9 GND AVCC REFHI RMIDA VINB RMIDB REFLO 1 2 3 4 5 6 7 8 9 10 11 12 13 14 ENCODE +VS GND GND +VS INA GND +VS VT REF A INB REF B VB NC MSB D5A D4A D3A D2A D1A LSB D0A GND +VS MSB D5B D4B D3B D2B D1B LSB D0B 28 27 26 25 24 23 22 21 20 19 18 17 16 15 A5 A4 A3 A2 A1 A0 GND AVCC B5 B4 B3 B2 B1 B0 A0 A1 A2 A3 A4 A5 9 8 7 6 5 4 3 2 U103 74AS574 8D 7D 6D 5D 4D 3D 2D 1D 8Q 7Q 6Q 5Q 4Q 3Q 2Q 1Q CLK 11 OE GND GND 12 13 14 15 16 17 18 19 GND GND A00 A00 A01 A02 A03 A04 A05 E9 1 A01 A02 A03 E11 A04 A05 CLK BIT0 3 BIT1 4 BIT2 5 BIT3 6 BIT4 7 BIT5 8 BIT6 9 BIT7 10 BIT8 11 BIT9 A02 A01 A00 +5V U105 74AS04 1 2 U105 74AS04 3 4 SMBPN J102 23 B05 24 REF 25 RS B04 B03 COMP +5V B02 B01 B00 GND 21 GND E4 B0 B1 B2 B3 B4 B5 9 8 7 6 5 4 3 2 U104 74AS574 8D 8Q 7D 7Q 6D 6Q 5D 5Q 4D 4Q 3D 3Q 2D 2Q 1D 1Q CLK OE 11 12 13 14 15 16 17 18 19 3 4 38 5 37 36 6 7 35 34 8 9 33 10 32 31 11 12 30 29 13 14 28 27 15 26 16 17 25 24 18 19 23 22 20 21 E5 R110 100 B00 B01 B02 B03 B04 B05 U107 17 ADV7128R GND GND GND GND 1 B00 B01 B02 B03 B04 VINA R102 49.9 E6 RECONSTRUCT A C30 0.1µF BGND GND AGND GND B05 CLK 2 BIT0 3 BIT1 4 BIT2 5 BIT3 +5V 6 BIT4 7 C105 BIT5 8 0.1µF BIT6 9 23 BIT7 COMP 10 24 BIT8 REF 11 25 BIT9 RS 1 R108 560 ANALOG B SMBPN J104 BUFLAT BUFLAT C105 0.1µF R109 560 BUFLAT GND GND +5V C104 0.1µF E10 ANALOG A SMBPN J103 2 A04 A03 H40DM J105 40 39 1 2 C40 0.1µF SMBPN J101 CR101 AD589H 2 21 GND2 GND3 GND1 GND4 VINB R101 49.9 RECONSTRUCT B R107 100 DVCC +5V + C1 10µF C10 0.1µF C11 0.1µF C12 0.1µF C13 0.1µF C14 0.1µF C15 0.1µF C16 0.1µF C17 0.1µF C18 0.1µF C19 0.1µF C50 0.1µF C51 0.1µF GND AVCC + AVCC C2 10µF C20 0.1µF C21 0.1µF C23 0.1µF C108 0.1µF GND Figure 9. Customer Evaluation Board Schematic Evaluation Board Operation The analog inputs provided to the evaluation board are ac coupled to the AD9066. Since the input range is centered around 3.9 V, capacitors C30 and C40 are used to block the dc component and allow driving with an external low impedance signal generator or amplifier. The AD9066 is encoded with an external encode applied to J100. On the rising edge of the clock, the analog inputs to both halves of the converter are sampled and converted to a 6-bit digital word. This digital word is placed on the output pins of REV. 0 the DUT. The same rising edge that converts the data within the AD9066 is used to latch data latches U103 and U104. This effectively creates a one pipeline delay between the DUT and the external data interface and reconstruction DACs. Data from the data latches is routed to the interface and to the ADV7128 digital-to-analog converters. These are 10-bit CMOS converters. The lower 4 bits are tied to logic low. The current outputs of these devices are terminated into 100 ohms and routed to SMB connectors for external use. –7– C2019–10–4/95 AD9066 Figure 10. Evaluation Board–Mechanical Layout OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 28-Lead Small Outline Package (R-28) 28 15 0.2992 (7.60) 0.2914 (7.40) 14 1 0.1043 (2.65) 0.0926 (2.35) 0.7125 (18.10) 0.6969 (17.70) 0.0118 (0.30) 0.0040 (0.10) 0.0500 (1.27) BSC 0.4193 (10.65) 0.3937 (10.00) 0.0192 (0.49) 0.0138 (0.35) –8– 0.0125 (0.32) 0.0091 (0.23) PRINTED IN U.S.A. PIN 1 0.0291 (0.74) x 45 ° 0.0098 (0.25) 8° 0° 0.0500 (1.27) 0.0157 (0.40) REV. 0