a FEATURES 77 MSPS Encode Rate Bipolar Input Range Low Error Rate Overflow Bit MIL-STD-883 Compliant Versions Available High Speed 6-Bit A/D Converter AD9000 FUNCTIONAL BLOCK DIAGRAM APPLICATIONS QAM Telecommunications Electronic Warfare (ECM, ECCM, ESM) Radar Guidance Digitizers GENERAL DESCRIPTION The AD9000 is a 6-bit, high speed, analog-to-digital converter with ECL compatible outputs and a bipolar input stage. The AD9000 is fabricated in a high performance bipolar process that allows encode rates up to 77 MSPS. The AD9000 employs the standard flash converter architecture based on 64 individual comparators which simultaneously determine the precise analog signal level. The comparators are followed by two stages of decoding logic, allowing the AD9000 to operate with a very low error rate. The low 35 pF input capacitance of the AD9000 greatly simplifies the analog driver stage. An overflow output bit is also incorporated into the AD9000 design as is a hysteresis control pin to modify comparator sensitivity. The AD9000 is offered as both a commercial temperature range device, 0°C to +70°C, and as an extended temperature range device, –55°C to +125°C. Both versions are available packaged in a 16-pin ceramic DIP. The extended temperature range device is also available in a 28-pin ceramic LCC package. The extended temperature range versions are offered as fully compliant MIL-STD-883 Class B devices. REV. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 617/329-4700 World Wide Web Site: http://www.analog.com Fax: 617/326-8703 © Analog Devices, Inc., 1997 AD9000–SPECIFICATIONS(Supply Voltages = –5.2 V and +5.0 V; Differential Reference Voltage = 2.0 V ELECTRICAL CHARACTERISTICS unless otherwise noted) Commercial 08C to +708C AD9000JD Parameter Temp RESOLUTION DC ACCURACY Differential Linearity Integral Linearity No Missing Codes INITIAL OFFSET ERROR Top of Reference Ladder Bottom of Reference Ladder Offset Drift Coefficient ANALOG INPUT Input Voltage Range Input Bias Current (Sampling)1 Input Bias Current (Latched)1 Input Resistance Input Capacitance Full Power Bandwidth2 Min Typ Military –558C to +1258C AD9000SD/SE Max 6 Min Typ Max 6 Units Bits +25°C Full +25°C Full Full 0.25 0.5 1.0 0.25 0.5 1.0 GUARANTEED 0.25 0.5 1.0 0.25 0.5 1.0 GUARANTEED LSB LSB LSB LSB +25°C Full +25°C Full Full 0.3 0.3 LSB LSB LSB LSB µV/°C 0.25 0.25 145 ± 2.0 V 800 20 3.0 35 20 REFERENCE INPUT3, 4 Reference Ladder Resistance Ladder Temperature Coefficient Reference Input Bandwidth +25°C DYNAMIC PERFORMANCE5 Conversion Rate Conversion Time (+ 1 Clock) Aperture Delay (tD) Aperture Uncertainty (Jitter) Output Propagation Delay (tPD)6 Output Hold Time (tOH)7 Transient Response8 Overvoltage Recovery Time9 Output Rise Time10 Output Fall Time10 Output Time Skew +25°C +25°C +25°C +25°C +25°C +25°C +25°C +25°C +25°C +25°C +25°C 50 ENCODE INPUT Logic “l” Voltage Logic “0” Voltage Logic “1” Current Logic “0” Current Input Capacitance ENCODE Pulse Width High (tPWH) ENCODE Pulse Width Low (tPWL) Full Full Full Full +25°C +25°C +25°C –1.1 80 800 20 3.0 35 20 50 200 80 0.275 20 50 200 0.275 20 70 75 77 20 13.3 2 25 8 8 7/8 1.5 7/8 1.5 145 ± 2.0 V Full Full Full +25°C +25°C +25°C +25°C 7/8 1.5 7/8 1.5 2 25 12 14 8 8 13 11 12 14 13 11 5.0 5.0 4.5 4.5 0.4 0.4 –1.1 2.5 6.6 6.6 –1.5 100 100 5.0 2.5 6.6 6.6 –2– –1.5 100 100 5.0 V µA µA kΩ pF MHz Ω Ω/°C MHz MHz ns ns ps ns ns ns ns ns ns ns V V µA µA pF ns ns REV. A AD9000 ELECTRICAL CHARACTERISTICS (Continued) Commercial 08C to +708C AD9000JD Parameter Temp Min Typ Military –558C to +1258C AD9000SD/SE Max Min Typ Max Units 11 AC LINEARITY Dynamic Linearity12 In-Band Harmonics (DC to l MHz) (l MHz to 5 MHz) (5 MHz to 8 MHz) Signal-to-Noise Ratio13 Signal-to-Noise Ratio14 Two Tone Intermodulation Rejection15 Noise Power Ratio (NPR)16 +25°C 0.5 0.5 LSB +25°C +25°C +25°C +25°C +25°C +25°C +25°C 44 42 38 33 42 46 30 44 42 38 33 42 46 30 dBc dBc dBc dB dB dBc dBc DIGITAL OUTPUTS5 Logic “l” Voltage Logic “0” Voltage Full Full POWER SUPPLY17 Positive Supply Current (+5.0 V) Negative Supply Current (–5.2 V) Nominal Power Dissipation Reference Ladder Dissipation 31 40 31 40 –1.1 +25°C Full +25°C Full +25°C +25°C –1.1 –1 .5 60 68 675 20 70 75 80 85 –1.5 60 68 675 20 70 75 80 85 V V mA mA mA mA mW mW 9 NOTES 1 AIN = +VREF. 2 Determined by 3 dB reduction in reconstructed output at 75 MSPS. 3 Under normal operating conditions, the analog input voltages should not exceed nominal ± 2 V operating range, nor the supply voltages (+V S and –VS), whichever is smaller. 4 Under normal operating conditions the differential reference voltage may range from ± 0.5 V to ± 2 V; +VREF ≥ –VREF. 5 Output terminated with 100 Ω resistors to –2.0 V. 6 Measured from the leading edge of ENCODE to data out on Bit 1 (MSB). 7 Measured from the trailing edge of ENCODE to data out on Bit 1 (MSB). 8 For full-scale step input, 6-bit accuracy is attained in specified time. Recovers to 6-bit accuracy in specified time, after 150% full-scale input overvoltage. 10 Measured on Bit 1 (MSB) only. 11 Measured at 50 MSPS encode rate. 12 Analog input frequency = 15 MHz. 13 RMS signal to RMS noise, with 540 kHz analog input signal. 14 Peak-to-peak signal to rms noise, with 540 kHz analog input signal. 15 f1 = 9.3 MHz, f 2 = 7.6 MHz; Encode = 42 MHz. 16 DC to 8.2 MHz noise bandwidth with 3.886 MHz slot. 17 Supply voltage should remain stable within ± 5% for normal operation. ABSOLUTE MAXIMUM RATINGS 1 NOTES 1 Absolute maximum ratings are limiting values, to be applied individually, and beyond which serviceability of the circuit may be impaired. Functional operability under any of these conditions is not necessarily implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 Under normal operating conditions, the analog input voltages should not exceed nominal +2 V operating range, nor the supply voltages (+V S and –VS), whichever is smaller. 3 Under normal operating conditions the differential reference voltage may range from ± 0.5 V to ± 2 V; +VREF ≥ –VREF. 4 Typical thermal impedances . . . 16-Pin Ceramic θJA = 67°C/W; θJC = 7°C/W 28-Pin LCC θJA = 62°C/W; θJC = 14°C/W Positive Supply Voltage . . . . . . . . . . . . . . . . . . . 0.3 V to +6 V Negative Supply Voltage . . . . . . . . . . . . . . . . . 6.0 V to +0.3 V Analog-to-Digital Ground Voltage Differential . . . . . . . . . 0.5 Analog Input Voltages (AIN, +VREF, –VREF)2 . . . . . . . . . . +3 V Differential Reference Voltage (+VREF to –VREF)3 . . . . . . . 6 V ENCODE Input Voltage . . . . . . . . . . . . . . . . . . . . – VS to 0 V HYSTERESIS Control Voltage . . . . . . . . . . . . 0 V to + 3.0 V Digital Output Current . . . . . . . . . . . . . . . . . . . . . . . . 20 mA Power Dissipation (+25°C Free Air)4 . . . . . . . . . . . . 745 mW Operating Temperature Range AD9000JD . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C AD9000SD/SE . . . . . . . . . . . . . . . . . . . . . . –55°C to +125°C Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . +175°C Lead Soldering Temperature (10 sec) . . . . . . . . . . . . +300°C REV. A Specifications subject to change without notice. –3– AD9000 ORDERING GUIDE1 Device Temperature Range Description Package Option2 AD9000JD AD9000SD AD9000SE 0°C to +70°C –55°C to +125°C –55°C to +125°C 16-Pin DIP, Industrial 16-Pin DIP 28-Pin LCC D-16 D-16 E-28A NOTES 1 MIL-STD-883 versions available, contact factory. 2 D = Ceramic DIP; E = Leadless Ceramic Chip Carrier. PIN DESIGNATIONS DIE LAYOUT MECHANICAL INFORMATION Die Dimensions . . . . . . . . . . . . . . . . 129 × 217 × 15 (± 2) mils Pad Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 × 4 mils Metalization . . . . . . . . . . . . . . . . . . . . . . . 10,000Å Aluminum Backing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . None Substrate Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –VS Passivation . . . . . . . . . . . . . . . . . . . . . . . . 10,000Å Oxynitride Die Attach . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Gold Eutectic Bond Wire . . . . . . . . 1.25 mil Aluminum; Ultrasonic Bonding or 1 mil Gold; Gold Ball Bonding PIN DESCRIPTIONS Pin Name Description –VS Negative supply terminal, nominally –5.2 V. ANALOG GROUND Analog ground return. All grounds should be connected together near the AD9000. VH The hysteresis control voltage varies the comparator hysteresis from 15 mV to 50 mV, for a change of 0 V to +3 V at the hysteresis control pin. ENCODE The ENCODE pin controls the conversion cycle. Encode is rising edge sensitive and should be driven with a 50% duty-cycle waveform under normal conditions. –VREF The most negative reference voltage for the internal resistor ladder. AIN Analog input pin. +VS Positive supply terminal, nominally +5.0 V. +VREF Most positive reference voltage of the internal resistor ladder. BIT 6 (LSB) One of six digital outputs. BIT 6 (LSB) is the least-significant-bit of the digital output. BIT 5 – BIT 2 One of six digital outputs. BIT 1 (MSB) One of six digital outputs. BIT 1 (MSB) is the most-significant-bit of the digital output. OVERFLOW Overflow data output. Logic high indicates an input overvoltage (AIN ≥ +VREF). DIGITAL GROUND Digital ground return. All grounds should be connected together near the AD9000. CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD9000 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. –4– WARNING! ESD SENSITIVE DEVICE REV. A AD9000 Figure 1. Functional Block Diagram Figure 2. System Timing Diagram Figure 3. Burn-ln Test Circuit REV. A –5– AD9000 ABOUT THE AD9000 Analog Bandwidth Quantifying the high frequency analog performance of the AD9000 is somewhat difficult because of the various criteria that can be applied. At one extreme there is the analog input bandwidth of a single input comparator (which tends to be extremely high). At the other end of the performance criteria is the “no missing codes” restriction, which tends to be the most conservative measure of analog bandwidth. The “no missing codes” criteria simply means that the converter is capable of generating all 64 output codes for an analog and ENCODE frequency. At higher ENCODE rates to analog frequencies, the converter continues to function, but with reduced resolution. The graph below details the “no missing codes” region of operation for the AD9000 at several reference levels. Note that nearly all analog-to-digital converter applications operate in the oversampled region to avoid generation of indeterminate data (aliasing). Figure 5. Comparator Switching vs. Hysteresis Voltage Layout Considerations The AD9000, like all high-speed circuits, requires certain precautions be taken to ensure optimum performance. The foremost of these is the use of a substantial low impedance ground plane around and under the AD9000. Just as important are high quality ground connections to the AD9000 itself. It is probably more effective to keep the analog and digital grounds separate, except at the AD9000 where they should be connected together. Sockets should generally be avoided due to the increased interlead capacitance they induce. If socketing must be used, pin sockets are preferred. Decoupling is especially important to high-speed analog circuits. Each supply should be decoupled to ground with 0.1 µF ceramic and 0.001 µF mica capacitors. The ladder reference pins should be treated in a similar manner. In addition to decoupling the reference ladder, the reference ladder should be driven from a low output impedance source for the best noise rejection. In all cases where practical, chip capacitors are recommended to reduce the effects of lead inductance associated with standard discrete capacitors. Figure 4. Analog Input vs. Encode Rate “No Missing Codes” High-Speed Performance Enhancements MIL-STD-883 Compliance Information The AD9000 employs a hysteresis control pin which affects comparator sensitivity. The error rate (number of full-scale errors in a given period) is directly affected by the comparator sensitivity. By varying the voltage on the hysteresis control pin, the error rate can be reduced. The AD9000 is capable of extremely low error rate operation, which makes it ideal for error sensitive applications such as QAM demodulation. If the hysteresis control pin is used, it should be decoupled to ground through a 0.1 µF capacitor, otherwise it may be left floating. The AD9000SE/SD/883C are classified within microcircuits group 57-technology group D (bipolar A/D converters), and are constructed in accordance with the latest revision of MIL-STD883. The AD9000 is electrostatic sensitive and falls within electrostatic sensitivity classification Category A. PDA (Percent Defective Allowance) is computed based on Subgroups 1 of the specified Group A test list. QA screening is in accordance with “Alternate Method A” of method 5005. The following apply: Burn-In per 1015, Life Test per 1005, Electrical Testing per 5004. (Note: Group A electrical Testing assumes TA = TC = TJ.) At the highest encode rates, overall accuracy can be improved by skewing the ENCODE signal duty-cycle to allow more time in the “latch” mode. Specifically, extending the logic HIGH portion of the ENCODE signal allows the comparators more time to achieve an appropriate logic level prior to the decoding cycle that begins on the rising edge of the ENCODE pulse. –6– REV. A AD9000 TYPICAL APPLICATION The AD9000 is a relatively flexible device that can be configured in a number of ways. One very useful feature of the AD9000 is the open emitter outputs. The open emitters allow the outputs of several AD9000s to be OR-wired in stacking applications for increased resolution. This kind of application depends on the return-to-zero nature of the output bits when AIND≥ + VREF (overflow). In circuits that employ only one AD9000, this is not always an advantage. The circuit below illustrates one method of converting the outputs to nonreturnto-zero. The 10197 (standard 10K ECL logic) hex-AND group senses the active OVERFLOW output and forces all other bits to logic HIGH. The 10151 latch is not required for AD9000 applications, but it may ease data transfer sensitivities in asynchronous data collection systems. The reference driver circuits should provide a low source impedance to prevent noise on the reference inputs from affecting the AD9000’s accuracy. This is accomplished to a large extent by adequately decoupling the reference pins to ground. An improved method is employed below. The reference voltages (+VREF, –VREF) are buffered by a transistor/amplifier combination. This has the advantages of wide bandwidth (hence low impedance over a wide frequency range to eliminate high frequency noise components), and improved temperature stability. Figure 6. REV. A –7– Inputs to the AD9000/PCB evaluation board include the analog signal to be digitized, as well as an optional ENCODE input for high stability measurements. All components, except the AD9000, are soldered onto the 8.5" × 6.3" board. The AD9000 is socketed to facilitate moderate volume testing. The evaluation board is offered with either a commercial temperature range AD9000, or an extended temperature range device installed. AD9000/PCB EVALUATION AND TEST BOARD Evaluating and testing the AD9000 is greatly simplified with the AD9000/PCB evaluation board. The printed circuit board contains all of the driver and buffering circuits needed to test and evaluate the AD9000. The board outputs include both a high quality reconstructed representation of the input waveform, and a dc error waveform output that can be used to determine device linearities. The respective ordering numbers are AD9000JD/PCB and AD9000SD/PCB. C807a–21–8/87 AD9000 Figure 7. PCB Block Diagram OUTLINE DIMENSIONS Dimensions shown in inches and (mm). –8– PRINTED IN U.S.A. 28-Pin LCC 16-Pin Ceramic REV. A