74AC00, 74ACT00
Quad 2-Input NAND Gate
Features

General Description

■ ICC reduced by 50%

The AC00/ACT00 contains four, 2-input NAND gates.

■ Outputs source/sink 24mA
■ ACT00 has TTL-compatible inputs

Ordering Information
Order
Number

Package
Number

Package Description

74AC00SC

M14A

14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow

74AC00SJ

M14D

14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

74AC00MTC

MTC14

14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
Wide

74AC00PC

N14A

14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide

74ACT00SC

M14A

14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow

M14D

14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

74ACT00SJ
74ACT00MTC
74ACT00PC

MTC14
N14A

14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
Wide
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide

Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number.
All packages are lead free per JEDEC: J-STD-020B standard.

Connection Diagram

Logic Symbol
IEEE/IEC

Pin Description
Pin Names

Description

An, Bn

Inputs

On

Outputs

©1988 Fairchild Semiconductor Corporation
74AC00, 74ACT00 Rev. 1.4.1

www.fairchildsemi.com

74AC00, 74ACT00 — Quad 2-Input NAND Gate

January 2008

Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.

Symbol
VCC
IIK

Parameter

Rating

Supply Voltage

–0.5V to +7.0V

DC Input Diode Current
VI = –0.5V

–20mA

VI = VCC + 0.5

+20mA

VI

DC Input Voltage

–0.5V to VCC + 0.5V

IOK

DC Output Diode Current
VO = –0.5V

–20mA

VO = VCC + 0.5V

+20mA

VO

DC Output Voltage

–0.5V to VCC + 0.5V

IO

DC Output Source or Sink Current

±50mA

ICC or IGND DC VCC or Ground Current per Output Pin

±50mA

TSTG

Storage Temperature

–65°C to +150°C

TJ

Junction Temperature

140°C

Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to absolute maximum ratings.

Symbol
VCC

Parameter

Rating

Supply Voltage
AC

2.0V to 6.0V

ACT

4.5V to 5.5V

VI

Input Voltage

0V to VCC

VO

Output Voltage

0V to VCC

TA

Operating Temperature

∆V / ∆t

–40°C to +85°C
125mV/ns

Minimum Input Edge Rate, AC Devices:
VIN from 30% to 70% of VCC, VCC @ 3.3V, 4.5V, 5.5V

∆V / ∆t

125mV/ns

Minimum Input Edge Rate, ACT Devices:
VIN from 0.8V to 2.0V, VCC @ 4.5V, 5.5V

©1988 Fairchild Semiconductor Corporation
74AC00, 74ACT00 Rev. 1.4.1

www.fairchildsemi.com
2

74AC00, 74ACT00 — Quad 2-Input NAND Gate

Absolute Maximum Ratings

Symbol
VIH

Parameter
Minimum HIGH Level
Input Voltage

VCC
(V)
3.0

TA = +25°C
Conditions
VOUT = 0.1V
or VCC – 0.1V

Maximum LOW Level
Input Voltage

VOH

Units

2.1

2.1

2.25

3.15

3.15

2.75

3.85

3.85

1.5

0.9

0.9

2.25

1.35

1.35

2.75

1.65

1.65

2.99

2.9

2.9

4.5

4.49

4.4

4.4

5.5

5.49

5.4

5.4

2.56

2.46

3.86

3.76

4.86

4.76

0.002

0.1

0.1

4.5

0.001

0.1

0.1

5.5

0.001

0.1

0.1

0.36

0.44

0.36

0.44

0.36

0.44

±0.1

±1.0

µA

4.5
3.0
4.5

VOUT = 0.1V
or VCC – 0.1V

5.5
Minimum HIGH Level
Output Voltage

Guaranteed Limits

1.5

5.5
VIL

Typ.

TA = –40°C to +85°C

3.0

3.0

IOUT = –50µA

VIN = VIL or VIH,

V

V

V

IOH = –12mA
4.5

VIN = VIL or VIH,
IOH = –24mA

5.5

VIN = VIL or VIH,
IOH =

VOL

Maximum LOW Level
Output Voltage

3.0

3.0

–24mA(1)

IOUT = 50µA

VIN = VIL or VIH,

V

IOL = 12mA
4.5

VIN = VIL or VIH,
IOL = 24mA

5.5

VIN = VIL or VIH,
IOL =

IIN

(3)

IOLD
IOHD
ICC

(3)

24mA(1)

Maximum Input
Leakage Current

5.5

VI = VCC, GND

Minimum Dynamic
Output Current(2)

5.5

VOLD = 1.65V Max.

75

mA

5.5

VOHD = 3.85V Min.

–75

mA

5.5

VIN = VCC or GND

20.0

µA

Maximum Quiescent
Supply Current

2.0

Notes:
1. All outputs loaded; thresholds on input associated with output under test.
2. Maximum test duration 2.0ms, one output loaded at a time.
3. IIN and ICC @ 3.0V are guaranteed to be less than or equal to the respective limit @ 5.5V VCC.

©1988 Fairchild Semiconductor Corporation
74AC00, 74ACT00 Rev. 1.4.1

www.fairchildsemi.com
3

74AC00, 74ACT00 — Quad 2-Input NAND Gate

DC Electrical Characteristics for AC

Symbol
VIH
VIL
VOH

Parameter

VCC
(V)

Conditions

Typ.

TA = –40°C to +85°C
Guaranteed Limits

VOUT = 0.1V or
VCC – 0.1V

1.5

2.0

2.0

1.5

2.0

2.0

VOUT = 0.1V or
VCC – 0.1V

1.5

0.8

0.8

5.5

1.5

0.8

0.8

4.5

IOUT = –50µA

4.49

4.4

4.4

Minimum HIGH Level
Input Voltage

5.5

Maximum LOW Level
Input Voltage
Minimum HIGH Level
Output Voltage

TA = +25°C

4.5
4.5

5.5
4.5

5.49
VIN = VIL or VIH,

5.4

5.4

3.86

3.76

4.86

4.76

0.1

0.1

Units
V
V
V

IOH = –24mA
5.5

VIN = VIL or VIH,
IOH = –24mA(4)

VOL

Maximum LOW Level
Output Voltage

4.5

IOUT = 50µA

0.001

5.5
4.5

0.001
VIN = VIL or VIH,

0.1

0.1

0.36

0.44

0.36

0.44

±0.1

±1.0

V

IOL = 24mA
5.5

VIN = VIL or VIH,
IOL= 24mA(4)

IIN

Maximum Input
Leakage Current

5.5

VI = VCC, GND

µA

ICCT

Maximum ICC/Input

5.5

VI = VCC – 2.1V

1.5

mA

IOLD

Minimum Dynamic
Output Current(5)

5.5

VOLD = 1.65V Max.

75

mA

5.5

VOHD = 3.85V Min.

–75

mA

Maximum Quiescent
Supply Current

5.5

VIN = VCC or GND

20.0

µA

IOHD
ICC

0.6

2.0

Notes:
4. All outputs loaded; thresholds on input associated with output under test.
5. Maximum test duration 2.0ms, one output loaded at a time.

©1988 Fairchild Semiconductor Corporation
74AC00, 74ACT00 Rev. 1.4.1

www.fairchildsemi.com
4

74AC00, 74ACT00 — Quad 2-Input NAND Gate

DC Electrical Characteristics for ACT

TA = +25°C,
CL = 50pF
Symbol
tPLH
tPHL

Parameter
Propagation Delay
Propagation Delay

TA = –40°C to +85°C,
CL = 50pF

VCC (V)(6)

Min.

Typ.

Max.

Min.

Max.

Units

3.3

2.0

7.0

9.5

2.0

10.0

ns

5.0

1.5

6.0

8.0

1.5

8.5

3.3

1.5

5.5

8.0

1.0

8.5

5.0

1.5

4.5

6.5

1.0

7.0

ns

Note:
6. Voltage range 3.3 is 3.3V ± 0.3V. Voltage range 5.0 is 5.0V ± 0.5V.

AC Electrical Characteristics for ACT
TA = +25°C,
CL = 50pF
Symbol

Parameter

TA = –40°C to +85°C,
CL = 50pF

VCC (V)(7)

Min.

Typ.

Max.

Min.

Max.

Units

tPLH

Propagation Delay

5.0

1.5

5.5

9.0

1.0

9.5

ns

tPHL

Propagation Delay

5.0

1.5

4.0

7.0

1.0

8.0

ns

Note:
7. Voltage Range 5.0 is 5.0V ± 0.5V.

Capacitance
Symbol

Parameter

Conditions

Typ.

Units

CIN

Input Capacitance

VCC = OPEN

4.5

pF

CPD

Power Dissipation Capacitance

VCC = 5.0V

30.0

pF

©1988 Fairchild Semiconductor Corporation
74AC00, 74ACT00 Rev. 1.4.1

www.fairchildsemi.com
5

74AC00, 74ACT00 — Quad 2-Input NAND Gate

AC Electrical Characteristics for AC

8.75
8.50

0.65

A

7.62
14

8

B

5.60
4.00
3.80

6.00

PIN ONE
INDICATOR

1

1.70

7

0.51
0.35

1.27

0.25

1.27

LAND PATTERN RECOMMENDATION
M

C B A

(0.33)

1.75 MAX
1.50
1.25

SEE DETAIL A

0.25
0.10

C

0.25
0.19

0.10 C
NOTES: UNLESS OTHERWISE SPECIFIED
A) THIS PACKAGE CONFORMS TO JEDEC
MS-012, VARIATION AB, ISSUE C,
B) ALL DIMENSIONS ARE IN MILLIMETERS.
C) DIMENSIONS DO NOT INCLUDE MOLD
GAGE PLANE
FLASH OR BURRS.
D) LANDPATTERN STANDARD:
SOIC127P600X145-14M
0.36
E) DRAWING CONFORMS TO ASME Y14.5M-1994
F) DRAWING FILE NAME: M14AREV13

0.50 X 45°
0.25
R0.10
R0.10
8°
0°

0.90
0.50
(1.04)

SEATING PLANE

DETAIL A
SCALE: 20:1

Figure 1. 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,
specifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/
©1988 Fairchild Semiconductor Corporation
74AC00, 74ACT00 Rev. 1.4.1

www.fairchildsemi.com
6

74AC00, 74ACT00 — Quad 2-Input NAND Gate

Physical Dimensions

74AC00, 74ACT00 — Quad 2-Input NAND Gate

Physical Dimensions (Continued)

Figure 2. 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,
specifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/

©1988 Fairchild Semiconductor Corporation
74AC00, 74ACT00 Rev. 1.4.1

www.fairchildsemi.com
7

74AC00, 74ACT00 — Quad 2-Input NAND Gate

Physical Dimensions (Continued)

0.65

0.43 TYP

1.65

6.10

0.45

12.00° TOP

& BOTTOM

R0.09 min

A. CONFORMS TO JEDEC REGISTRATION MO-153,
VARIATION AB, REF NOTE 6
B. DIMENSIONS ARE IN MILLIMETERS
C. DIMENSIONS ARE EXCLUSIVE OF BURRS, MOLD FLASH,
AND TIE BAR EXTRUSIONS
D. DIMENSIONING AND TOLERANCES PER ANSI
Y14.5M, 1982
E. LANDPATTERN STANDARD: SOP65P640X110-14M
F. DRAWING FILE NAME: MTC14REV6

1.00

R0.09min

Figure 3. 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,
specifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/

©1988 Fairchild Semiconductor Corporation
74AC00, 74ACT00 Rev. 1.4.1

www.fairchildsemi.com
8

74AC00, 74ACT00 — Quad 2-Input NAND Gate

Physical Dimensions (Continued)
19.56
18.80
14

8

6.60
6.09
1

7

(1.74)

8.12
7.62

1.77
1.14

3.56
3.30

0.35
0.20

5.33 MAX
0.38 MIN

3.81
3.17

0.58
0.35

8.82

2.54

NOTES: UNLESS OTHERWISE SPECIFIED
THIS PACKAGE CONFORMS TO
A) JEDEC MS-001 VARIATION BA
B) ALL DIMENSIONS ARE IN MILLIMETERS.
DIMENSIONS ARE EXCLUSIVE OF BURRS,
C) MOLD FLASH, AND TIE BAR EXTRUSIONS.
D) DIMENSIONS AND TOLERANCES PER
ASME Y14.5-1994
E) DRAWING FILE NAME: MKT-N14AREV7
Figure 4. 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,
specifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/

©1988 Fairchild Semiconductor Corporation
74AC00, 74ACT00 Rev. 1.4.1

www.fairchildsemi.com
9

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* EZSWITCH™ and FlashWriter® are trademarks of System General Corporation, used under license by Fairchild Semiconductor.
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FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS
HEREIN TO IMPROVE RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE
APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS
PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. THESE SPECIFICATIONS DO NOT EXPAND THE TERMS OF FAIRCHILD’S
WORLDWIDE TERMS AND CONDITIONS, SPECIFICALLY THE WARRANTY THEREIN, WHICH COVERS THESE PRODUCTS.
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FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR
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As used herein:
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which, (a) are intended for surgical implant into the body or
(b) support or sustain life, and (c) whose failure to perform
when properly used in accordance with instructions for use
provided in the labeling, can be reasonably expected to
result in a significant injury of the user.

2. A critical component in any component of a life support,
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PRODUCT STATUS DEFINITIONS
Definition of Terms
Datasheet Identification

Product Status

Definition

Advance Information

Formative or In Design

This datasheet contains the design specifications for product
development. Specifications may change in any manner without notice.

Preliminary

First Production

This datasheet contains preliminary data; supplementary data will be
published at a later date. Fairchild Semiconductor reserves the right to
make changes at any time without notice to improve design.

No Identification Needed

Full Production

This datasheet contains final specifications. Fairchild Semiconductor
reserves the right to make changes at any time without notice to improve
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Obsolete

Not In Production

This datasheet contains specifications on a product that has been
discontinued by Fairchild Semiconductor. The datasheet is printed for
reference information only.
Rev. I32

©1988 Fairchild Semiconductor Corporation
74AC00, 74ACT00 Rev. 1.4.1

www.fairchildsemi.com
10

74AC00, 74ACT00 — Quad 2-Input NAND Gate

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