MP7684 CMOS 8-Bit High Speed Analog-to-Digital Converter FEATURES BENEFITS • • • • • • • • • • • • Sampling Rates from 0.001 to 15 MHz (MSPS) 1/2 LSB (K Grade) DNL to 6 MHz Interface to any Input Range between GND and VDD Monotonic; No Missing Codes Single Power Supply (4 to 6 volt) Low Power CMOS (300 mW) 2000 Volts ESD Protection Latch-Up Free Low Power for Lower System Noise Most Flexible Input Range of any A/D Available No Sample/Hold Needed Use MP7684A for New Designs GENERAL DESCRIPTION sets VREF(–) and VREF(+) to encompass the desired input range. The MP7684 is an 8-bit monolithic CMOS single step high speed Analog-to-Digital Converter designed for precision applications in video and data acquisition requiring conversion rates to 10 MHz with differential linearity error less than 1/2 LSB and low power consumption. A unique feature of this converter is its input architecture which eliminates the need for an input track and hold and allows full scale input ranges from 1.2 to 5 volts peak-to-peak, referred to ground or offset. The user simply The MP7684 includes 256 clocked comparators, encoders, 3-state output buffers, a reference resistor ladder and associated timing circuitry. An overflow bit (or flag) has been provided to make it possible to achieve 9-bit resolution by connecting two devices in parallel. In normal operation this flag has no effect on the data bits. SIMPLIFIED BLOCK AND TIMING DIAGRAM AVDD VIN DVDD OE2 COFW VREF(+) OFW 1/2 R C255 R 9 3/4 R 1/2 R Ladder 1/4 R Encoder R Mux DFF OE1 φS φ B C1 R VREF(–) 1/2 R CLK DB7-DB0 8 φ B φS φB φS AGND CLK φS CLK DGND Rev. 2.00 1 DB7-DB0 N N MP7684 ORDERING INFORMATION Part No. DNL (LSB) –40 to +85°C MP7684JN 1 1/2 2 Plastic Dip –40 to +85°C MP7684KN 1 1/2 SOIC –40 to +85°C 1 MP7684JS 2 –40 to +85°C 1 1/2 SOIC MP7684KS 1 1/2 Ceramic Dip –40 to +85°C 1 Package Type Temperature Range Plastic Dip INL (LSB) –40 to +85°C MP7684JD 1 1/2 2 Ceramic Dip MP7684KD 1 1/2 Ceramic Dip –55 to +125°C 1 MP7684SD* 2 Ceramic Dip –55 to +125°C 1 1/2 MP7684TD* 1 1 1/2 *Contact factory for availability PIN CONFIGURATIONS See Packaging Section for Package Dimensions CLK DB7 DB6 DB5 DB4 1/4 R DVDD DGND 3/4 R DB3 DB2 DB1 DB0 OFW 1 28 2 27 3 26 4 25 5 24 6 23 7 22 8 21 9 20 10 19 11 18 12 17 13 16 14 15 VIN VREF(–) AVDD AGND AGND AVDD 1/2 R AVDD AGND AGND AVDD VREF(+) OE1 OE2 1 28 2 27 3 26 4 25 5 6 7 8 28 Pin PDIP, CDIP (0.600”) N28, D28 24 See Pin Out at Left 23 22 21 9 20 10 19 11 18 12 17 13 16 14 15 28 Pin SOIC (EIAJ, 0.335”) R28 Rev. 2.00 2 MP7684 PIN OUT DEFINITIONS PIN NO. NAME DESCRIPTION 1 CLK Clock Input Pin 2 DB7 Data Output Bit 7 (MSB) 3 DB6 Data Output Bit 6 4 DB5 Data Output Bit 5 5 DB4 Data Output Bit 4 6 1/4R 1/4 of Resistance Ladder 7 DVDD Power Supply of Digital Circuit 8 DGND Digital Ground 9 3/4R 3/4 of Resistance Ladder 10 DB3 Data Output Bit 3 11 DB2 Data Output Bit 2 12 DB1 Data Output Bit 1 13 DB0 Data Output Bit 0 (LSB) 14 OFW Digital Output Overflow Pin 15 OE2 Output Enable Control Pin 16 OE1 Output Enable Control Pin 17 VREF(+) Positive Reference Voltage Pin 18 AVDD Power Supply of Analog Circuit 19 AGND Analog Circuit Ground 20 AGND Analog Circuit Ground 21 AVDD Power Supply of Analog Circuit 22 1/2R Center of Resistance Ladder 23 AVDD Power Supply of Analog Circuit 24 AGND Analog Ground 25 AGND Analog Ground 26 AVDD Power Supply of Analog Circuit 27 VREF(–) Negative Reference Voltage Pin 28 VIN Analog Input Rev. 2.00 3 MP7684 ELECTRICAL CHARACTERISTICS TABLE Unless Otherwise Specified: AVDD = DVDD = 5 V, FS = 10 MHz (Duty Cycle: 1/3 Sample & 2/3 Balance), VREF(+) = +4.1 V, VREF(–) = AGND, TA = 25°C Parameter Symbol Min FS 8 0.1 25°C Typ Max Tmin to Tmax Min Max Units Test Conditions/Comments KEY FEATURES Resolution Sampling Rate 6 8 0.1 6 Bits MHz +1 1/2 2 LSB LSB For Specified Accuracy ACCURACY (J, S Grades)1 Differential Non-Linearity Integral Non-Linearity (Relative Accuracy) Zero Scale Error Full Scale Error DNL INL +3/4 1 1/2 EZS EFS 2 2 Best Fit Line (Max INL – Min INL) / 2 LSB LSB ACCURACY (K, T Grades)1 Differential Non-Linearity Integral Non-Linearity Zero Scale Error Full Scale Error DNL INL EZS EFS +1/2 1 +1 1 1/2 2 2 LSB LSB LSB LSB DYNAMIC ACCURACY2 Differential Non-Linearity Best Fit Line Histogram Test DNL +0.3 LSB FIN = 390 kHz REFERENCE VOLTAGES Positive Ref. Voltage3 Negative Ref. Voltage Ladder Resistance Ladder Temp. Coefficient2 VREF(+) VREF(–) RL RTCO AVDD AGND 120 AVDD 400 AGND 90 VREF(+) VREF(–) 430 3000 V V Ω ppm/°C ANALOG INPUT2 Input Voltage Range Input Capacitance Sample4 Input Impedance Aperture Delay Aperture Uncertainty (Jitter) VIN VREF(–) CIN ZIN tAP tAJ VREF(+) 50 10 25 60 V p-p pF MΩ ns ps DIGITAL INPUTS Logical “1” Voltage Logical “0” Voltage Leakage Currents5 CLK OE17 OE26 Input Capacitance2 Clock Timing (See Figure 1.) Duty Cycle VIH VIL IIN 3.5 3.5 1.5 1.5 100 50 1 +100 75 1 V V 5 µA µA µA pF 50 % –100 –1 –60 Rev. 2.00 4 –1 –100 VIN=DGND to DVDD MP7684 ELECTRICAL CHARACTERISTICS TABLE (CONT’D) Description Symbol Min 25°C Typ Max Tmin to Tmax Min Max Units COUT=15 pF DIGITAL OUTPUTS Logical “1” Voltage Logical “0” Voltage Off Current Output Capacitance2 3-state Leakage Data Hold Time (See Figure 1.)2 Data Valid Delay2 Data Enable Delay2 Data 3-state Delay2 Conditions VOH VOL IOFF CO IOZ tHLD tDL tDEN tDHZ 4.3 VDD IDD 4 4.3 +1 5 1 50 55 40 40 0.6 10 0.6 +1.5 (typ) 10 10 V V µA pF µA ns ns ns ns 6 90 V mA ILOAD = –1.0 mA ILOAD = 2.0 mA VOUT=DGND to DVDD POWER SUPPLIES9 (Tmin to Tmax) Operating Voltage (AVDD, DVDD) Current (AVDD + DVDD) 6 75 4 NOTES Tester measures code transitions by dithering the voltage of the analog input (VIN). The difference between the measured and the ideal code width (VREF/256) is the DNL error (Figure 3.). The INL error is the maximum distance (in LSBs) from the best fit line to any transition voltage (Figure 4.). Accuracy is a function of the sampling rate (FS). 2 Guaranteed. Not tested. 3 Specified values guarantee functionality. Refer to other parameters for accuracy. 4 See VIN input equivalent circuit (Figure 5.). Switched capacitor analog input requires driver with low output resistance. 5 All inputs have diodes to DVDD and DGND. Input OE1 has internal pull down. Input OE2 has internal pull up. Input DC currents will not exceed specified limits for any input voltage between DGND and DVDD. 6 Internal resistor to DVDD biases unconnected input to active high logical level. 7 Internal resistor to GND biases unconnected input to active low logical level. 8 Condition to meet aperture delay specifications (tAP, tAJ). Actual rise/fall time can be less stringent with no loss of accuracy. 9 DVDD and AVDD are connected through the silicon substrate. Connect together at the package and to the analog supply. 1 Specifications are subject to change without notice ABSOLUTE MAXIMUM RATINGS (TA = +25°C unless otherwise noted)1, 2, 3 Storage Temperature . . . . . . . . . . . . . . . . . . . –65 to +150°C Lead Temperature (Soldering 10 seconds) . . . . . . . +300°C Package Power Dissipation Rating to 75°C CDIP, PDIP, SOIC, LCC . . . . . . . . . . . . . . . . . . . 1050mW Derates above 75°C . . . . . . . . . . . . . . . . . . . . . 14mW/°C VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7 V VREF(+) & VREF(–) . . . . . . . . . . . . . . GND –0.5 to VDD +0.5 V VIN . . . . . . . . . . . . . . . . . . . . . . . . . . GND –0.5 to VDD +0.5 V All Inputs . . . . . . . . . . . . . . . . . . . . . GND –0.5 to VDD +0.5 V All Outputs . . . . . . . . . . . . . . . . . . . GND –0.5 to VDD +0.5 V NOTES: (1) Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation at or above this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. (2) Any input pin which can see a value outside the absolute maximum ratings should be protected by Schottky diode clamps (HP5082-2835) from input pin to the supplies. All inputs have protection diodes which will protect the device from short transients outside the supplies of less than 100mA for less than 100µs. (3) VDD refers to AVDD and DVDD. GND refers to AGND and DGND. Rev. 2.00 5 MP7684 tR tS tB tF V IH CLOCK OE1 VIH VIL V IL SAMPLE N–1 AUTO BALANCE SAMPLE N AUTO BALANCE SAMPLE N+1 OE2 VIL VIH tDEN ANALOG INPUT tDEN tDHZ DB7–DB0 tDHZ Hi-Z DATA DATA DATA VOH DATA N N-1 VOL Hi-Z OFW tDL DATA DATA tHLD Figure 1. MP7684 Timing Diagram DNL Figure 2. Output Enable/Disable Timing Diagram Output Codes LSB Best Fit Line 7 V(N+1) Real Transfer Line Analog Input 6 V(N) 5 EFS INL N+1 Output Codes 4 N Ideal Transfer Line 3 N–1 (N) Code Width = V(N+1) – V(N) LSB = [ VREF(+) – VREF(–) ] / 256 2 LSB 1 DNL(N) = [ V(N+1) – V(N) ] – LSB Analog Input (Volt) EZS Figure 3. DNL Measurement Figure 4. INL Error Calculation AVDD Clock 10 Ω Low High VIN + 30 pF 20 pF 1/2 V REF AGND Figure 5. Analog Input Equivalent Circuit Rev. 2.00 6 MP7684 LSB. That is if (dv/dt) ∗ tAJ ≈ VREF/256, an internal error of 1 LSB results. THEORY OF OPERATION Analog-to-Digital Conversion Accuracy of Conversion: DNL and INL The MP7684 converts analog voltages into 256 digital codes by encoding the outputs of 255 comparators. A 256th comparator is used to generate the overflow bit. The conversion is synchronous with the clock and it is accomplished in 1.5 clock periods. Data is transferred from the comparator latches to the output registers each clock period and at the same time the input is sampled. The transfer function for an ideal A/D converter is shown in Figure 7. DIGITAL CODES 0.5 ∗ LSB The clock signal generates the two internal phases, φB (CLK high = balance) and φS (CLK low = sample). φB connects the comparators to the reference tap points. φS connects the comparators to the analog input voltage. φS 0 2 01 00 FD LSB V VREF(–) V01 V02 VFE VFF V0FW VREF(+) Figure 7. Ideal A/D Transfer Function φS The overflow transition (V0FW) takes place at: VIN VIN = V0FW = VREF(+) – 0.5 ∗ LSB Latch The first and the last transitions for the data bits take place at: VTAP Ref Ladder FF FE VREF = VREF(+) – VREF(–) = 256 ∗ LSB φB OFW = 1 OFW = 0 1 LSB The reference resistance ladder is a series of 257 resistors. The first and the last resistor of the ladder are half the value of the others so that the following relations apply: RREF = 256 ∗ R 0.5 ∗ LSB VIN = V01 = VREF(–) + 0.5 ∗ LSB φB VIN = VFF = VREF(–) – 1.5 ∗ LSB COMPARATOR LSB = (VREF(+) – VREF(–) / 256 = (VFF – V01) / 254 Note that the overflow transition is a flag and has no impact on the data bits. Figure 6. MP7684 Comparator The MP7684 comparators use the balance phase (φB) to charge one plate of the capacitors to the reference ladder tap point (VTAP) and the other to the inverter/comparator trigger point. During the sample phase (φS) one plate of the capacitors switches to VIN . The change in voltage (VIN – VTAP) transfers across the capacitor and forces the inverter into one of the two possible logic states. A latch (connected to the comparator during φS) restores and propagates the digital level to the encode logic. DIGITAL CODES 0.5 ∗ LSB 1.5 ∗ LSB EFS EZS FF FE 02 01 00 VREF(–) V01 The rising edge of the CLK input marks the end of the sampling phase (φS). Internal delay of the clock circuitry will delay the actual instant when φS disconnects the latch from the comparator. This delay is called aperture delay (tAP). V02 VFE VFF V VREF(+) Figure 8. Real A/D Transfer Curve In a “real” converter, the code-to-code transitions do not fall exactly every ( VREF(+) – VREF(–) ) / 256 volts. The aperture delay is not constant but changes from one cycle to the next. Internal thermal noise, power supply noise and slow input clock edges are major contributors to this variation. The aperture jitter (tAJ) is the variation of the aperture delay distribution. A positive DNL (Differential Non Linearity) error means that the real width of a particular code is larger than 1 LSB. This error is measured in fractions of LSB’s. A Max DNL specification guarantees that ALL code widths (DNL errors) are within the stated value. A specification of Max DNL = + 0.5 LSB means that all codes are within 0.5 and 1.5 This uncertainty shows as digital code errors if the input slew rate multiplied by tAJ is of the same order of magnitude as the Rev. 2.00 7 MP7684 LSB. If VREF = 4.096 V then 1 LSB = 16mV and every code width is within 8 and 24 mV. Clock Timing The formulas for Differential Non-linearity (DNL), Integral Non-Linearity (INL) and zero and full scale errors (EZS, EFS) are: A system will clock the MP7684 continuously (Figure 9a.) or it will give clock pulses intermittently when a conversion is desired. The timing of Figure 9b. keeps the MP7684 comparators in balance and ready to sample the analog input. This mode draws the most current from VDD. The timing of Figure 9c. leaves the comparator inputs floating (and AC coupled to the VIN input) and a balance phase is needed before a valid sampling phase. In this mode, IDD varies because of the floating comparator inputs. DNL (01) = V02 – V01 – LSB : : : DNL (FE) = VFF – VFE – LSB EFS (full scale error) = VFF – [VREF(+) –1.5 ∗ LSB] EZS (zero scale error) = V01 – [VREF(–) + 0.5 ∗ LSB] Analog Input Figure 4. shows the zero scale and full scale error terms. Systems that adjust the VREF voltages to correct for EFS and EZS only increase the accuracy at the two extreme points. In the MP7684, such adjustments have little impact at frequencies lower than 10 MHz. Refer to the characterization data for temperature and frequency dependence. The MP7684 has very flexible input range characteristics. The user sets VREF(+) and VREF(–) to fixed voltages and then varies the input DC and AC levels to match the VREF range. Another method is to first design the analog input circuitry and then adjust the reference voltages for the analog input range. One advantage is that this approach may eliminate the need for external gain and offset adjust circuitry which may be required by fixed input range A/Ds. Figure 4. gives a visual definition of the INL error. The chart shows a 3-bit converter transfer curve with greatly exaggerated DNL errors to show the deviation of the real transfer curve from the ideal one. The MP7684’s performance is optimized by using analog input circuitry that is capable of driving the AIN input. These have an impact above 5 MHz and they are very important above 10 MHz. Use of Current Feedback Amplifiers is an easy and cost effective way to maximize performance. After a tester has measured all the transition voltages, a line is drawn parallel to the ideal transfer line. By definition the Best Fit Line makes equal the positive and the negative INL errors. This may change an INL of –1 to +2 LSB’s relative to the Ideal Line into a +1.5 relative to the Best Fit Line. Reference Voltages SAMPLE BAL N CLOCK DATA If the input bandwidth is limited to the Nyquist region (FIN < FS/2) then the two reference voltages can be set at any two values between the supplies. VREF (their difference) can be reduced down to 1.5 volts with minor change in accuracy. If the input bandwidth exceeds FS/2, then it is recommended that VREF be lower than VDD/2. N a. Two positive clock pulses CLOCK N At VREF = 1.5 V, the LSB is reduced to 6mV. Further reductions show an increased error in terms of LSB (which is getting smaller) even if the error in terms of mV remains constant. BALANCE The input/output relationship as a function of VREF: N DATA AIN = (VIN – VREF(–)) DATA = 256 ∗ (AIN/VREF) b. Two negative clock pulses CLOCK N DATA N+1 a) Gain adjustment. A system can increase total gain by reducing VREF. N+2 N N+1 b) Increasing dynamic range. A system can increase dynamic range by using DAC’s to control VREF and by “focusing” on input ranges of interest. In digitizing “static” information (an image in a scanner), a first digitization would point to the input range in which most of the output codes fall. The system then would adjust the DACs to generate VREF(+) and VREF(–) to include just the range of interest for the second and final pass. N+2 c. Continuous clock Figure 9. Relationship of Data to Clock Rev. 2.00 8 MP7684 c) Subranging; increasing resolution. Where practical, multiple passes at different VREF ranges can increase resolution without changing hardware. A system needs to make four passes to increase the resolution to 10 bits. The merging of the data from the four passes can create DNL errors at the borders of the ranges. One solution is to “overlap” the ranges and to use software methods to properly merge the ranges. If a latch follows the ADC, the positive half of the clock used as enable signal guarantees stable output at the end of the enable pulse. DB7–DB0 φS VIN A/D Latch E L7–L0 DFF F7–F0 DFF Digital Interfaces MP7684 CLK The logic encodes the 255 bits into a binary code and latches the data in a D-type flip-flop for output. The inputs OE1 and OE2 control the output buffers in an asynchronous mode. CLK OE1 OE2 OFW DB7 – DB0 X 0 High Z High Z tDL 1 1 Valid High Z DB7-DB0 0 1 Valid Valid VIN L7-L0 N N+1 tHLD N-1 N-2 N N-1 N Table 1. Output Enable Logic F7-F0 If another DFF is to follow the ADC, it is recommended that the system latches the data at the negative going edge of the clock. This will work at any frequency. If the system must latch with the positive going edge, then care must be taken to avoid the overlay of the clock edge with the changing outputs. N-2 N-1 N Figure 10. MP7684 Functional Equivalent Circuit and Interface Timing Rev. 2.00 9 MP7684 APPLICATION NOTES AVDD DIGITAL GROUND DVDD DGND +V C1 C2 (Note 7) C1 C2 ANALOG GROUND C1, C2 Rt DB7 - DB0 C1, C2 +V – 20kΩ MP7684 2k 10pF + VREF(+) C2 C1 MP5010 C1 C2 C1 = 0.1µF CLK 10 C1 Rt C2 = 10µF Rt = Line Termination Resistor 3/4 R 1/2 R To Digital System OE1 OE2 –V 1k AGND OFW VIN (Substrate) 225Ω 1/4 R C1 VREF(–) AGND DGND Figure 11. Typical Circuit Connections 1. All signals should not exceed AVDD +0.5 V or AGND –0.5 V or DVDD +0.5 V. 6. Analog and digital ground planes should be substantial and common at one point only. The ground plane should act as a shield for parasitics and not a return path for signals. To reduce noise levels, use separate low impedance ground paths. 2. Any input pin which can see a value outside the absolute maximum ratings (AVDD or DVDD+0.5 V or AGND –0.5 V) should be protected by diode clamps (HP5082-2835) from input pin to the supplies. All MP7684A inputs have input protection diodes which will protect the device from short transients outside the supply ranges. 7. DVDD should not be shared with other digital circuitry. DVDD for the MP7684 should be connected to AVDD next to the MP7684. 8. DVDD and AVDD are connected inside the MP7684 through the N – doped silicon substrate. DC voltage differences between DVDD and AVDD will cause undesirable internal currents. 3. The design of a PC board will affect the accuracy of MP7684. Use of wire wrap is not recommended. 4. The analog input signal (VIN) is quite sensitive and should be properly routed and terminated. It should be shielded from the clock and digital outputs to minimize cross coupling and noise pickup. 9. The power supplies and reference voltages should be decoupled with a ceramic (0.1µF) and a tantalum (10µF) capacitor as close to the device as possible. 10. The digital output should not drive long wires. The capacitive coupling and reflection will contribute noise to the conversion. When driving distant loads, buffers should be used. 5. The analog input should be driven by a buffer op amp with as low output impedance as possible. The impedance should be less than 50Ω for clock frequencies above 10 MHz. Rev. 2.00 10 MP7684 Rev. 2.00 11 MP7684 Rev. 2.00 12 MP7684 28 LEAD PLASTIC DUAL-IN-LINE (600 MIL PDIP) N28 S 28 15 E1 1 14 Q1 E D A1 Seating Plane A L B e B1 α MILLIMETERS INCHES SYMBOL A MIN MAX MIN MAX –– 0.232 –– 5.893 A1 0.015 –– 0.381 –– B 0.014 0.023 0.356 0.584 B1 (1) 0.038 0.065 0.965 1.65 C 0.008 0.015 0.203 0.381 D 1.380 1.490 35.05 37.85 E 0.585 0.625 14.86 15.88 E1 0.500 0.610 12.70 15.49 e 0.100 BSC L 0.115 α 0.150 2.54 BSC 2.92 3.81 0° 15° 0° 15° Q1 0.055 0.070 1.40 1.78 S 0.020 0.100 1.508 2.54 Note: (1) The minimum limit for dimensions B1 may be 0.023” (0.58 mm) for all four corner leads only. Rev. 2.00 13 C MP7684 28 LEAD CERAMIC DUAL-IN-LINE (600 MIL CDIP) D28 S S1 28 15 1 14 See Note 1 E1 E D Q Base Plane Seating Plane A L c e b INCHES SYMBOL A L1 b1 NOTES MILLIMETERS MIN MAX MIN MAX –– 0.232 –– 5.89 NOTES –– b 0.014 0.023 0.356 0.584 –– b1 0.038 0.065 0.965 1.65 2 c 0.008 0.015 0.203 0.381 –– D –– 1.490 –– 37.85 4 E 0.500 0.610 12.70 15.49 4 E1 0.590 0.620 14.99 15.75 7 e 0.100 BSC 2.54 BSC 5 L 0.125 0.200 3.18 5.08 –– L1 0.150 –– 3.81 –– –– Q 0.015 0.060 0.381 1.52 3 S –– 0.100 –– 2.54 6 0.005 –– 0.13 –– 6 0° 15° 0° 15° –– S1 α α Rev. 2.00 14 1. Index area; a notch or a lead one identification mark is located adjacent to lead one and is within the shaded area shown. 2. The minimum limit for dimension b1 may be 0.023 (0.58 mm) for all four corner leads only. 3. Dimension Q shall be measured from the seating plane to the base plane. 4. This dimension allows for off-center lid, meniscus and glass overrun. 5. The basic lead spacing is 0.100 inch (2.54 mm) between centerlines. 6. Applies to all four corners. 7. This is measured to outside of lead, not center. MP7684 28 LEAD SMALL OUTLINE (335 MIL EIAJ SOIC) R28 D 28 15 E 1 H 14 C A Seating Plane e B A1 L MILLIMETERS SYMBOL A A1 MIN 2.60 INCHES MAX MIN 2.80 0.102 0.2 (typ.) MAX 0.110 0.008 (typ.) B 0.3 0.5 0.012 0.020 C 0.10 0.20 0.004 0.008 D 17.6 18.0 0.693 0.709 E 8.3 8.5 0.327 0.335 e 1.27 (typ.) 0.050 (typ.) H 11.5 12.1 0.453 0.477 L 0.8 1.2 0.031 0.047 Rev. 2.00 15 MP7684 NOTICE EXAR Corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contains here in are only for illustration purposes and may vary depending upon a user’s specific application. While the information in this publication has been carefully checked; no responsibility, however, is assumed for inaccuracies. EXAR Corporation does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corporation is adequately protected under the circumstances. Copyright EXAR Corporation Datasheet April 1995 Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited. Rev. 2.00 16