STP22NF03L
N-channel 30 V, 0.0038 Ω, 22 A, TO-220
STripFET™ II Power MOSFET
Features
Type

VDSS

RDS(on) max

ID

STP22NF03L

30 V

< 0.05 Ω

22 A

■

Exceptional dv/dt capability

■

Low gate charge at 100°C

■

Application oriented characterization

■

100% avalanche tested

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Application
■

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Switching applications

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Figure 1.

Description

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This Power MOSFET is the latest development of
STMicroelectronics unique "single feature size"
strip-based process. The resulting transistor
shows extremely high packing density for low onresistance, rugged avalanche characteristics and
less critical alignment steps therefore a
remarkable manufacturing reproducibility.

1

3

2

TO-220

Internal schematic diagram

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Table 1.

Device summary

Order code

Marking

Package

Packaging

STP22NF03L

P22NF03L@

TO-220

Tube

October 2008

Rev 5

1/12
www.st.com

12

Contents

STP22NF03L

Contents
1

Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

2

Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.1

Electrical characteristics (curves)

............................. 6

3

Test circuit

................................................ 8

4

Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

5

Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

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STP22NF03L

1

Electrical ratings

Electrical ratings
Table 2.

Absolute maximum ratings

Symbol
VDS
VDGR

Parameter

Value

Unit

Drain-source voltage (VGS = 0)

30

V

Drain-gate voltage (RGS = 20 kΩ)

30

V

± 15

V
A

Gate- source voltage

VGS
ID

Drain current (continuous) at TC = 25 °C

22

ID(1)

Drain current (continuous) at TC = 100 °C

16

Drain current (pulsed)

88

Total dissipation at TC = 25 °C

45

IDM(1)
Ptot

EAS

(3)

Single pulse avalanche energy

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Storage temperature

Tstg

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Max. operating junction temperature

Tj

P
e

Peak diode recovery voltage slope

1. Pulse width limited by safe operating area.

A

ct

du

ro

Derating factor
dv/dt(2)

(s)
A

W

0.3

W/°C

6

V/ns

200

mJ

-55 to 175

°C

Value

Unit

2. ISD ≤ 22 A, di/dt ≤ 300 A/µs, VDD ≤ V(BR)DSS, Tj ≤ TJMAX

)
(s

3. Starting Tj = 25 °C, ID = 11 A, VDD = 15 V

Table 3.

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Thermal data

Rthj-case

od

Thermal resistance junction-case max

3.33

°C/W

Rthj-amb

Thermal resistance junction-ambient max

62.5

°C/W

Maximum lead temperature for soldering purpose

300

°C

Symbol

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TJ

Pr

Parameter

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Electrical characteristics

2

STP22NF03L

Electrical characteristics
(TCASE = 25 °C unless otherwise specified)
Table 4.

On/off states

Symbol

Parameter

Test conditions

V(BR)DSS

Drain-source
breakdown voltage

ID = 250 µA, VGS =0

IDSS

Zero gate voltage
drain current (VGS = 0)

VDS = max ratings
VDS = max ratings,
TC = 125 °C

IGSS

Gate-body leakage
current (VDS = 0)

VGS = ± 20 V

VGS(th)

Gate threshold voltage

VDS = VGS, ID = 250 µA

RDS(on)

Static drain-source on
resistance

VGS = 10 V, ID = 11 A
VGS = 5 V, ID = 11 A

Table 5.

Parameter

gfs (1)

Forward
transconductance

Ciss
Coss
Crss

Input capacitance
Output capacitance
Reverse transfer
capacitance

td(on)
tr
td(off)
tf

bs

Qg
Qgs
Qgd

O

)-

Unit
V

1
10

µA
µA

±100

nA

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1

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0.038
0.045

0.05
0.06

Ω
Ω

Min.

Typ.

Max.

Unit

7

S

VDS = 25 V, f = 1 MHz,
VGS = 0

330
90
40

pF
pF
pF

Turn-on delay time
Rise time
Turn-off delay time
Fall time

VDD = 15 V, ID = 11 A
RG = 4.7 Ω VGS = 5 V
(see Figure 13)

13
4
12
5

ns
ns
ns
ns

Total gate charge
Gate-source charge
Gate-drain charge

VDD = 24 V, ID = 22 A,
VGS = 5 V
(see Figure 14)

6.5
3.6
2

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1. Pulsed: Pulse duration = 300 µs, duty cycle 1.5%.

4/12

Max.

VDS= 15 V , ID = 11 A

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Test conditions

Typ.

30

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Dynamic

Symbol

Min.

9

nC
nC
nC

STP22NF03L

Electrical characteristics

Table 6.
Symbol

Source drain diode
Parameter

ISDM (1)

Source-drain current
Source-drain current
(pulsed)

VSD (2)

Forward on voltage

ISD

Test conditions

Min.

Typ.

ISD = 22 A, VGS = 0

ISD = 22 A,
Reverse recovery time
di/dt = 100 A/µs,
Reverse recovery charge
VDD = 15 V, Tj = 150 °C
Reverse recovery current
(see Figure 15)

trr
Qrr
IRRM

30
18
1.2

Max.

Unit

22
88

A
A

1.5

V
ns
nC
A

)
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ct

1. Pulse width limited by safe operating area.
2. Pulsed: Pulse duration = 300 µs, duty cycle 1.5%

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Electrical characteristics

STP22NF03L

2.1

Electrical characteristics (curves)

Figure 2.

Safe operating area

Figure 3.

Thermal impedance

AM01526v1

n)
(o

100µs

DS

Op
Lim era
ite tion
d
by in th
m is a
ax
R re

a

is

ID
(A)

10

1ms
10ms

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1

0.1
0.1

Figure 4.

10

1

100

u
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VDS(V)

Output characteristics

Figure 5.

Transfer characteristics

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Figure 6.

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Transconductance

Figure 7.

Static drain-source on resistance

STP22NF03L
Figure 8.

Electrical characteristics

Gate charge vs. gate-source voltage Figure 9.

Figure 10. Normalized gate threshold voltage
vs. temperature

Capacitance variations

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Figure 11. Normalized on resistance vs.
temperature

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Figure 12. Source-drain diode forward
characteristics

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Test circuit

3

STP22NF03L

Test circuit

Figure 13. Switching times test circuit for
resistive load

Figure 14. Gate charge test circuit
VDD
12V

47kΩ

1kΩ

100nF
3.3
µF

2200

RL

µF

IG=CONST

VDD

VGS

100Ω

Vi=20V=VGMAX

VD
RG

2200
µF

D.U.T.

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t

VG

2.7kΩ

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PW
47kΩ
1kΩ

PW

D.U.T.

AM01468v1

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AM01469v1

Figure 15. Test circuit for inductive load
Figure 16. Unclamped Inductive load test
switching and diode recovery times
circuit

A

A

D.U.T.

FAST
DIODE

B

B

A

D
G
S

s
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t
c
3.3
µF

B

25 Ω

D

1000
µF

RG

S

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2200
µF

3.3
µF

VDD

ID

Vi

D.U.T.

Pw

let

AM01470v1

Figure 17. Unclamped inductive waveform

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O

L

VD

VDD

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G

so

)-

L=100µH

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AM01471v1

Figure 18. Switching time waveform
ton

V(BR)DSS

tdon

VD

toff
tr

tdoff

tf

90%

90%
IDM

10%
ID
VDD

10%

0
VDD

VDS
90%

VGS

AM01472v1

8/12

0

10%

AM01473v1

STP22NF03L

4

Package mechanical data

Package mechanical data
In order to meet environmental requirements, ST offers these devices in ECOPACK®
packages. These packages have a Lead-free second level interconnect. The category of
second level interconnect is marked on the package and on the inner box label, in
compliance with JEDEC Standard JESD97. The maximum ratings related to soldering
conditions are also marked on the inner box label. ECOPACK is an ST trademark.
ECOPACK specifications are available at: www.st.com

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Package mechanical data

STP22NF03L

TO-220 mechanical data

mm

inch

Dim
Min
A
b
b1
c
D
D1
E
e
e1
F
H1
J1
L
L1
L20
L30
∅P
Q

3.75
2.65

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10/12

Min

4.60
0.88
1.70
0.70
15.75

0.173
0.024
0.044
0.019
0.6

10.40
2.70
5.15
1.32
6.60
2.72
14
3.93

0.393
0.094
0.194
0.048
0.244
0.094
0.511
0.137

Typ

Max
0.181
0.034
0.066
0.027
0.62

0.050

16.40
28.90

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Max

1.27
10
2.40
4.95
1.23
6.20
2.40
13
3.50

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(s

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Typ

4.40
0.61
1.14
0.48
15.25

b
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so

let

r
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3.85
2.95

u
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0.147
0.104

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0.409
0.106
0.202
0.051
0.256
0.107
0.551
0.154

0.645
1.137
0.151
0.116

STP22NF03L

5

Revision history

Revision history
Table 7.

Document revision history

Date

Revision

Changes

09-Sep-2004

1

Datasheet according to PCN DSG-TRA/04/532

09-Aug-2006

2

New template, no content change

20-Feb-2007

3

Typo mistake on page 1

03-Sep-2007

4

Figure 2: Safe operating area has been update.

08-Oct-2008

5

Figure 2: Safe operating area has been update.

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STP22NF03L

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Please Read Carefully:

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Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the
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