Features
• Low-voltage and Standard-voltage Operation
•
•
•
•
•
•
•
•
•
•
•

– 2.7 (VCC = 2.7V to 5.5V)
– 1.8 (VCC = 1.8V to 3.6V)
Internally Organized 65,536 x 8
2-wire Serial Interface
Schmitt Triggers, Filtered Inputs for Noise Suppression
Bidirectional Data Transfer Protocol
1 MHz (5V), 400 kHz (2.7V) and 100 kHz (1.8V) Compatibility
Write Protect Pin for Hardware and Software Data Protection
128-byte Page Write Mode (Partial Page Writes Allowed)
Self-timed Write Cycle (5 ms Typical)
High Reliability
– Endurance: 100,000 Write Cycles
– Data Retention: 40 Years
Automotive Grade and Extended Temperature Devices Available
8-lead PDIP, 8-lead EIAJ SOIC, 8-lead JEDEC SOIC, 8-lead TSSOP,
8-lead LAP and 8-ball dBGATM Packages

2-wire Serial
EEPROM
512K (65,536 x 8)

AT24C512

Description
The AT24C512 provides 524,288 bits of serial electrically erasable and programmable
read only memory (EEPROM) organized as 65,536 words of 8 bits each. The device’s
cascadable feature allows up to 4 devices to share a common 2-wire bus. The device
is optimized for use in many industrial and commercial applications where low-power
and low-voltage operation are essential. The devices are available in space-saving
8-pin PDIP, 8-lead EIAJ SOIC, 8-lead JEDEC SOIC, 8-lead TSSOP, 8-lead Leadless
Array (LAP) and 8-ball dBGA packages. In addition, the entire family is available in
2.7V (2.7V to 5.5V) and 1.8V (1.8V to 3.6V) versions.
8-lead PDIP

Pin Configurations
Pin Name

Function

A0 - A1

Address Inputs

SDA

Serial Data

SCL

Serial Clock Input

WP

Write Protect

NC

No Connect
8-lead TSSOP
A0
A1
NC
GND

1
2
3
4

8
7
6
5

VCC
WP
SCL
SDA

A0
A1
NC
GND

8
7
6
5

1
2
3
4

VCC
WP
SCL
SDA

8-lead Leadless Array
VCC
WP
SCL
SDA

8
7
6
5

1
2
3
4

A0
A1
NC
GND

Bottom View
8-ball dBGA

8-lead SOIC
A0
A1
NC
GND

1
2
3
4

8
7
6
5

VCC
WP
SCL
SDA

VCC
WP
SCL
SDA

8

1

7

2

6

3

5

4

A0
A1
NC
GND

Bottom View

Rev. 1116I–SEEPR–3/03

1

Absolute Maximum Ratings*
Operating Temperature.................................. -55°C to +125°C
Storage Temperature ..................................... -65°C to +150°C
Voltage on Any Pin
with Respect to Ground .....................................-1.0V to +7.0V
Maximum Operating Voltage .......................................... 6.25V

*NOTICE:

Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.

DC Output Current........................................................ 5.0 mA

Block Diagram

2

AT24C512
1116I–SEEPR–3/03

AT24C512
Pin Description

SERIAL CLOCK (SCL): The SCL input is used to positive edge clock data into each
EEPROM device and negative edge clock data out of each device.
SERIAL DATA (SDA): The SDA pin is bidirectional for serial data transfer. This pin is
open-drain driven and may be wire-ORed with any number of other open-drain or open
collector devices.
DEVICE/PAGE ADDRESSES (A1, A0): The A1 and A0 pins are device address inputs
that are hardwired or left not connected for hardware compatibility with AT24C128/256.
When the pins are hardwired, as many as four 512K devices may be addressed on a
single bus system (device addressing is discussed in detail under the Device Addressing section). When the pins are not hardwired, the default A1 and A0 are zero.
WRITE PROTECT (WP): The write protect input, when tied to GND, allows normal write
operations. When WP is tied high to VCC, all write operations to the memory are inhibited. If left unconnected, WP is internally pulled down to GND. Switching WP to VCC prior
to a write operation creates a software write protect function.

Memory Organization

AT24C512, 512K SERIAL EEPROM: The 512K is internally organized as 512 pages of
128-bytes each. Random word addressing requires a 16-bit data word address.

3
1116I–SEEPR–3/03

Pin Capacitance(1)
Applicable over recommended operating range from TA = 25°C, f = 1.0 MHz, VCC = +1.8V.
Symbol

Test Condition

CI/O
CIN
Note:

Max

Units

Conditions

Input/Output Capacitance (SDA)

8

pF

VI/O = 0V

Input Capacitance (A 0, A1, SCL)

6

pF

VIN = 0V

1. This parameter is characterized and is not 100% tested.

DC Characteristics
Applicable over recommended operating range from: TAI = -40°C to +85°C, VCC = +1.8V to +5.5V, TAC = 0°C to +70°C,
VCC = +1.8V to +5.5V (unless otherwise noted).
Symbol

Parameter

VCC1

Supply Voltage

VCC2

Max

Units

1.8

3.6

V

Supply Voltage

2.7

5.5

V

VCC3

Supply Voltage

4.5

5.5

V

ICC1

Supply Current

VCC = 5.0V

READ at 400 kHz

1.0

2.0

mA

ICC2

Supply Current

VCC = 5.0V

WRITE at 400 kHz

2.0

3.0

mA

Standby Current
(1.8V option)

VCC = 1.8V

1.0

µA

ISB1

ISB2

Standby Current
(2.7V option)

ISB3

Standby Current
(5.0V option)

VCC = 4.5 - 5.5V

ILI

Input Leakage Current

VIN = VCC or VSS

ILO

Output Leakage
Current

VOUT = VCC or VSS

VIL

Input Low Level(1)

VIH

Input High Level(1)

VOL2

Output Low Level

VCC = 3.0V

VOL1

Output Low Level

VCC = 1.8V

Note:

4

Test Condition

VCC = 3.6V
VCC = 2.7V
VCC = 5.5V

Min

Typ

VIN = VCC or VSS

3.0
2.0

VIN = VCC or VSS

µA

6.0

VIN = VCC or VSS

6.0

µA

0.10

3.0

µA

0.05

3.0

µA

-0.6

VCC x 0.3

V

VCC x 0.7

VCC + 0.5

V

IOL = 2.1 mA

0.4

V

IOL = 0.15 mA

0.2

V

1. VIL min and VIH max are reference only and are not tested.

AT24C512
1116I–SEEPR–3/03

AT24C512
AC Characteristics
Applicable over recommended operating range from TA = -40°C to +85°C, VCC = +1.8V to +5.5V, C L = 100 pF (unless otherwise noted). Test conditions are listed in Note 2.
1.8-volt
Min

Parameter

fSCL

Clock Frequency, SCL

tLOW

Clock Pulse Width Low

4.7

1.3

0.4

µs

tHIGH

Clock Pulse Width High

4.0

1.0

0.4

µs

tAA

Clock Low to Data Out Valid

0.1

tBUF

Time the bus must be free before a new
transmission can start(1)

4.7

1.3

0.5

µs

tHD.STA

Start Hold Time

4.0

0.6

0.25

µs

tSU.STA

Start Set-up Time

4.7

0.6

0.25

µs

tHD.DAT

Data In Hold Time

0

0

0

µs

tSU.DAT

Data In Set-up Time

200

100

100

ns

Inputs Rise Time

Min

100

(1)

(1)

4.5

Max

5.0-volt

Symbol

tR

Max

2.7-volt

Min

400

0.05

0.9

0.05

Max

Units

1000

kHz

0.55

µs

1.0

0.3

0.3

µs

300

300

100

ns

tF

Inputs Fall Time

tSU.STO

Stop Set-up Time

4.7

0.6

0.25

µs

tDH

Data Out Hold Time

100

50

50

ns

tWR

Write Cycle Time

Endurance
Notes:

(1)

5.0V, 25°C, Page Mode

20
100K

10
100K

10
100K

ms
Write Cycles

1. This parameter is characterized and is not 100% tested.
2. AC measurement conditions:
RL (connects to VCC): 1.3 kΩ (2.7V, 5V), 10 kΩ (1.8V)
Input pulse voltages: 0.3VCC to 0.7VCC
Input rise and fall times: ≤50 ns
Input and output timing reference voltages: 0.5VCC

5
1116I–SEEPR–3/03

Device Operation

CLOCK and DATA TRANSITIONS: The SDA pin is normally pulled high with an external device. Data on the SDA pin may change only during SCL low time periods (refer to
Data Validity timing diagram). Data changes during SCL high periods will indicate a start
or stop condition as defined below.
START CONDITION: A high-to-low transition of SDA with SCL high is a start condition
which must precede any other command (refer to Start and Stop Definition timing
diagram).
STOP CONDITION: A low-to-high transition of SDA with SCL high is a stop condition.
After a read sequence, the stop command will place the EEPROM in a standby power
mode (refer to Start and Stop Definition timing diagram).
ACKNOWLEDGE: All addresses and data words are serially transmitted to and from the
EEPROM in 8-bit words. The EEPROM sends a zero during the ninth clock cycle to
acknowledge that it has received each word.
STANDBY MODE: The AT24C512 features a low power standby mode which is
enabled: a) upon power-up and b) after the receipt of the STOP bit and the completion
of any internal operations.
MEMORY RESET: After an interruption in protocol, power loss or system reset, any 2wire part can be reset by following these steps:
(a) Clock up to 9 cycles, (b) look for SDA high in each cycle while SCL is high and then
(c) create a start condition as SDA is high.

6

AT24C512
1116I–SEEPR–3/03

AT24C512
Bus Timing (SCL: Serial Clock, SDA: Serial Data I/O)

Write Cycle Timing (SCL: Serial Clock, SDA: Serial Data I/O)

(1)

Note:

1. The write cycle time tWR is the time from a valid stop condition of a write sequence to the end of the internal clear/write cycle.

7
1116I–SEEPR–3/03

Data Validity

Start and Stop Definition

Output Acknowledge

8

AT24C512
1116I–SEEPR–3/03

AT24C512
Device Addressing

The 512K EEPROM requires an 8-bit device address word following a start condition to
enable the chip for a read or write operation (refer to Figure 1). The device address word
consists of a mandatory one, zero sequence for the first five most significant bits as
shown. This is common to all 2-wire EEPROM devices.
The 512K uses the two device address bits A1, A0 to allow as many as four devices on
the same bus. These bits must compare to their corresponding hardwired input pins.
The A1 and A0 pins use an internal proprietary circuit that biases them to a logic low
condition if the pins are allowed to float.
The eighth bit of the device address is the read/write operation select bit. A read operation is initiated if this bit is high and a write operation is initiated if this bit is low.
Upon a compare of the device address, the EEPROM will output a zero. If a compare is
not made, the device will return to a standby state.
DATA SECURITY: The AT24C512 has a hardware data protection scheme that allows
the user to write protect the whole memory when the WP pin is at VCC.

Write Operations

BYTE WRITE: A write operation requires two 8-bit data word addresses following the
device address word and acknowledgment. Upon receipt of this address, the EEPROM
will again respond with a zero and then clock in the first 8-bit data word. Following
receipt of the 8-bit data word, the EEPROM will output a zero. The addressing device,
such as a microcontroller, then must terminate the write sequence with a stop condition.
At this time the EEPROM enters an internally-timed write cycle, tWR, to the nonvolatile
memory. All inputs are disabled during this write cycle and the EEPROM will not
respond until the write is complete (refer to Figure 2).
PAGE WRITE: The 512K EEPROM is capable of 128-byte page writes.
A page write is initiated the same way as a byte write, but the microcontroller does not
send a stop condition after the first data word is clocked in. Instead, after the EEPROM
acknowledges receipt of the first data word, the microcontroller can transmit up to 127
more data words. The EEPROM will respond with a zero after each data word received.
The microcontroller must terminate the page write sequence with a stop condition (refer
to Figure 3).
The data word address lower 7 bits are internally incremented following the receipt of
each data word. The higher data word address bits are not incremented, retaining the
memory page row location. When the word address, internally generated, reaches the
page boundary, the following byte is placed at the beginning of the same page. If more
than 128 data words are transmitted to the EEPROM, the data word address will “roll
over” and previous data will be overwritten. The address “roll over” during write is from
the last byte of the current page to the first byte of the same page.
ACKNOWLEDGE POLLING: Once the internally-timed write cycle has started and the
EEPROM inputs are disabled, acknowledge polling can be initiated. This involves sending a start condition followed by the device address word. The read/write bit is
representative of the operation desired. Only if the internal write cycle has completed
will the EEPROM respond with a zero, allowing the read or write sequence to continue.

9
1116I–SEEPR–3/03

Read Operations

Read operations are initiated the same way as write operations with the exception that
the read/write select bit in the device address word is set to one. There are three read
operations: current address read, random address read and sequential read.
CURRENT ADDRESS READ: The internal data word address counter maintains the
last address accessed during the last read or write operation, incremented by one. This
address stays valid between operations as long as the chip power is maintained. The
address “roll over” during read is from the last byte of the last memory page, to the first
byte of the first page.
Once the device address with the read/write select bit set to one is clocked in and
acknowledged by the EEPROM, the current address data word is serially clocked out.
The microcontroller does not respond with an input zero but does generate a following
stop condition (refer to Figure 4).
RANDOM READ: A random read requires a “dummy” byte write sequence to load in the
data word address. Once the device address word and data word address are clocked
in and acknowledged by the EEPROM, the microcontroller must generate another start
condition. The microcontroller now initiates a current address read by sending a device
address with the read/write select bit high. The EEPROM acknowledges the device
address and serially clocks out the data word. The microcontroller does not respond
with a zero but does generate a following stop condition (refer to Figure 5).
SEQUENTIAL READ: Sequential reads are initiated by either a current address read or
a random address read. After the microcontroller receives a data word, it responds with
an acknowledge. As long as the EEPROM receives an acknowledge, it will continue to
increment the data word address and serially clock out sequential data words. When the
memory address limit is reached, the data word address will “roll over” and the sequential read will continue. The sequential read operation is terminated when the
microcontroller does not respond with a zero but does generate a following stop condition (refer to Figure 6).
Figure 1. Device Address

10

AT24C512
1116I–SEEPR–3/03

AT24C512
Figure 2. Byte Write

Figure 3. Page Write

Figure 4. Current Address Read

11
1116I–SEEPR–3/03

Figure 5. Random Read

Figure 6. Sequential Read

12

AT24C512
1116I–SEEPR–3/03

AT24C512

Ordering Information
Ordering Code

Package

AT24C512C1-10CI-2.7
AT24C512-10PI-2.7
AT24C512W-10SI-2.7
AT24C512N-10SI-2.7
AT24C512-10TI-2.7
AT24C512-10UI-2.7

8CN1
8P3
8S2
8S1
8A2
8U2

Industrial
(-40°C to 85°C)

AT24C512C1-10CI-1.8
AT24C512-10PI-1.8
AT24C512W-10SI-1.8
AT24C512N-10SI-1.8
AT24C512-10TI-1.8
AT24C512-10UI-1.8

8CN1
8P3
8S2
8S1
8A2
8U2

Industrial
(-40°C to 85°C)

Note:

Operation Range

For 2.7V devices used in the 4.5V to 5.5V range, please refer to performance values in the AC and DC characteristics tables.

Package Type
8CN1

8-lead, 0.300" Wide, Leadless Array Package (LAP)

8P3

8-lead, 0.300" Wide, Plastic Dual In-line Package (PDIP)

8S2

8-lead, 0.200” Wide, Plastic Gull Wing Small Outline Package (EIAJ SOIC)

8S1

8-lead, 0.150” Wide, Plastic Gull Wing Small Outline Package (JEDEC SOIC)

8A2

8-lead, 4.4 mm Body, Plastic Thin Shrink Small Outline Package (TSSOP)

8U2

8-ball, die Ball Grid Array Package (dBGA)
Options

-2.7

Low-voltage (2.7V to 5.5V)

-1.8

Low-voltage (1.8V to 3.6V)

13
1116I–SEEPR–3/03

Packaging Information
8CN1 – LAP

Marked Pin1 Indentifier

E

A
A1

D

Top View

Side View
Pin1 Corner

L1

0.10 mm
TYP

8

1

e

COMMON DIMENSIONS
(Unit of Measure = mm)

2

7

3

6

b
5

4

e1

L

Bottom View

SYMBOL

MIN

NOM

MAX

A

0.94

1.04

1.14

A1

0.30

0.34

0.38

b

0.36

0.41

0.46

D

7.90

8.00

8.10

E

4.90

5.00

5.10

e

1.27 BSC

e1

0.60 REF

NOTE

1

L

0.62

0.67

0.72

1

L1

0.92

0.97

1.02

1

Note: 1. Metal Pad Dimensions.

11/13/01

R

14

2325 Orchard Parkway
San Jose, CA 95131

TITLE
8CN1, 8-lead (8 x 5 x 1.04 mm Body), Lead Pitch 1.27 mm,
Leadless Array Package (LAP)

DRAWING NO.
8CN1

REV.
A

AT24C512
1116I–SEEPR–3/03

AT24C512
8P3 – PDIP
E

1

E1

N

Top View

c
eA

End View

COMMON DIMENSIONS
(Unit of Measure = inches)

D
e
D1

A2 A

MIN

NOM

A2

0.115

0.130

0.195

b

0.014

0.018

0.022

5

b2

0.045

0.060

0.070

6

b3

0.030

0.039

0.045

6

c

0.008

0.010

0.014

D

0.355

0.365

0.400

D1

0.005

E

0.300

0.310

0.325

4

E1

0.240

0.250

0.280

3

SYMBOL

A

b2
b3
b

4 PLCS

Side View

L

Notes:

0.210

0.100 BSC

eA

0.300 BSC
0.115

NOTE

2

3
3

e

L

MAX

0.130

4
0.150

2

1. This drawing is for general information only; refer to JEDEC Drawing MS-001, Variation BA for additional information.
2. Dimensions A and L are measured with the package seated in JEDEC seating plane Gauge GS-3.
3. D, D1 and E1 dimensions do not include mold Flash or protrusions. Mold Flash or protrusions shall not exceed 0.010 inch.
4. E and eA measured with the leads constrained to be perpendicular to datum.
5. Pointed or rounded lead tips are preferred to ease insertion.
6. b2 and b3 maximum dimensions do not include Dambar protrusions. Dambar protrusions shall not exceed 0.010 (0.25 mm).

01/09/02

R

2325 Orchard Parkway
San Jose, CA 95131

TITLE
8P3, 8-lead, 0.300" Wide Body, Plastic Dual
In-line Package (PDIP)

DRAWING NO.

REV.

8P3

B

15
1116I–SEEPR–3/03

8S2 – EIAJ SOIC

1

H

N

Top View
e

b

A

D
COMMON DIMENSIONS
(Unit of Measure = mm)

Side View
SYMBOL

C

A1
L
E

End View

NOM

MAX

NOTE

A

1.78

2.03

A1

0.05

0.33

b

0.35

0.51

5

C

0.18

0.25

5

D

5.13

5.38

E

5.13

5.41

H

7.62

8.38

L

0.51

e

Notes: 1.
2.
3.
4.
5.

MIN

2, 3

0.89
1.27 BSC

4

This drawing is for general information only; refer to EIAJ Drawing EDR-7320 for additional information.
Mismatch of the upper and lower dies and resin burrs aren't included.
It is recommended that upper and lower cavities be equal. If they are different, the larger dimension shall be regarded.
Determines the true geometric position.
Values b,C apply to pb/Sn solder plated terminal. The standard thickness of the solder layer shall be 0.010 +0.010/-0.005 mm.

5/2/02

R

16

2325 Orchard Parkway
San Jose, CA 95131

TITLE
8S2, 8-lead, 0.209" Body, Plastic Small
Outline Package (EIAJ)

DRAWING NO.

8S2

REV.
B

AT24C512
1116I–SEEPR–3/03

AT24C512
8S1 – JEDEC SOIC

3

2

1

H

N

Top View
e

B
A

D

COMMON DIMENSIONS
(Unit of Measure = mm)

Side View
A2
C

L

SYMBOL

MIN

NOM

MAX

A

–

–

1.75

B

–

–

0.51

C

–

–

0.25

D

–

–

5.00

E

–

–

4.00

e

E

End View

NOTE

1.27 BSC

H

–

–

6.20

L

–

–

1.27

Note: This drawing is for general information only. Refer to JEDEC Drawing MS-012 for proper dimensions, tolerances, datums, etc.

10/10/01

R

2325 Orchard Parkway
San Jose, CA 95131

TITLE
8S1, 8-lead (0.150" Wide Body), Plastic Gull Wing
Small Outline (JEDEC SOIC)

DRAWING NO.

REV.

8S1

A

17
1116I–SEEPR–3/03

8A2 – TSSOP
3

2 1

Pin 1 indicator
this corner

E1

E

L1

N
L

Top View

End View
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL

A

b

D

MIN

NOM

MAX

NOTE

2.90

3.00

3.10

2, 5

3, 5

E

e
D

A2

6.40 BSC

E1

4.30

4.40

4.50

A

–

–

1.20

A2

0.80

1.00

1.05

b

0.19

–

0.30

e

Side View

L

0.65 BSC
0.45

L1
Notes:

0.60

0.75

1.00 REF

1. This drawing is for general information only. Refer to JEDEC Drawing MO-153, Variation AA, for proper dimensions, tolerances,
datums, etc.
2. Dimension D does not include mold Flash, protrusions or gate burrs. Mold Flash, protrusions and gate burrs shall not exceed
0.15 mm (0.006 in) per side.
3. Dimension E1 does not include inter-lead Flash or protrusions. Inter-lead Flash and protrusions shall not exceed 0.25 mm
(0.010 in) per side.
4. Dimension b does not include Dambar protrusion. Allowable Dambar protrusion shall be 0.08 mm total in excess of the
b dimension at maximum material condition. Dambar cannot be located on the lower radius of the foot. Minimum space between
protrusion and adjacent lead is 0.07 mm.
5. Dimension D and E1 to be determined at Datum Plane H.
5/30/02

R

18

4

2325 Orchard Parkway
San Jose, CA 95131

TITLE
8A2, 8-lead, 4.4 mm Body, Plastic
Thin Shrink Small Outline Package (TSSOP)

DRAWING NO.
8A2

REV.
B

AT24C512
1116I–SEEPR–3/03

AT24C512
8U2 – dBGA

E

Pin 1 Mark
this corner

D

Top View
- Z -

7

2

COMMON DIMENSIONS
(Unit of Measure = mm)

Øb
0

.

1

5

M

Z

0

.

0

8

M

Z

X

Y

#

1

#

8

SYMBOL

MIN

NOM

D

3

#

6

d
D1
e

E1

5.10

D1

1.43 TYP

E

4

A2
A
A1

Bottom View
Side View

3.25

E1

1.25 TYP

e

0.75 TYP

d

0.75 TYP

A

0.90 REF

A1

0.49

0.52

0.55

A2

0.35

0.38

0.41

Øb

0.47

0.50

0.53

Notes: 1. These drawings are for general information only. No JEDEC Drawing to refer to for additional information.
2. Dimension is measured at the maximum solder ball diameter, parallel to primary datum Z.

TITLE
R

NOTE

#

5

MAX

1150 E. Cheyenne Mtn. Blvd.
Colorado Springs, CO 80906

02/04/02
DRAWING NO.

8U2, 8-ball 0.75 pitch, Die Ball Grid Array
Package (dBGA) AT24C512 (AT19870)

8U2

REV.
A

19
1116I–SEEPR–3/03

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