19-1236; Rev 0; 6/97 KIT ATION EVALU E L B AVAILA Low-Power, 90Msps, Dual 6-Bit ADC ____________________________Features ♦ Two Matched 6-Bit ADCs ♦ High Sampling Rate: 90Msps per ADC ♦ Low Power Dissipation: 350mW ♦ Excellent Dynamic Performance: 5.85 ENOB with 20MHz Analog Input 5.7 ENOB with 50MHz Analog Input ♦ ±1/4LSB INL and DNL (typ) ♦ Internal Bandgap Voltage Reference ♦ Internal Oscillator with Overdrive Capability ♦ 55MHz (-0.5dB) Bandwidth Input Amplifiers with True Differential Inputs ♦ User-Selectable Input Full-Scale Range (125mVp-p, 250mVp-p, or 500mVp-p) ♦ 1/4LSB Channel-to-Channel Offset Matching (typ) ♦ 0.1dB Gain and 0.5° Phase Matching (typ) ♦ Single-Ended or Differential Input Drive ♦ Flexible, 3.3V, CMOS-Compatible Digital Outputs ________________________Applications Direct Broadcast Satellite (DBS) Receivers VSAT Receivers ______________Ordering Information Wide Local Area Networks (WLANs) Cable Television Set-Top Boxes MAX1003CAX PART TEMP. RANGE PIN-PACKAGE 0°C to +70°C 36 SSOP Pin Configuration appears at end of data sheet. _________________________________________________________Functional Diagram IOCC+ IOCC- IIN+ IIN- INPUT AMP I ADC I VREF 6 OFFSET CORRECTION I GAIN QIN- CLOCK OUT MAX1003 VREF ADC Q QOCC+ DCLK TNK- OFFSET CORRECTION Q INPUT AMP Q DI0–DI5 TNK+ CLOCK DRIVER BANDGAP REFERENCE QIN+ 6 DATA BUFFER I 6 DATA BUFFER Q 6 DQ0–DQ5 QOCC- ________________________________________________________________ Maxim Integrated Products 1 For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800 MAX1003 _______________General Description The MAX1003 is a dual, 6-bit analog-to-digital converter (ADC) that combines high-speed, low-power operation with a user-selectable input range, an internal reference, and a clock oscillator. The dual parallel ADCs are designed to convert in-phase (I) and quadrature (Q) analog signals into two 6-bit, offset-binary-coded digital outputs at sampling rates up to 90Msps. The ability to directly interface with baseband I and Q signals makes the MAX1003 ideal for use in direct-broadcast satellite, VSAT, and QAM16 demodulation applications. The MAX1003 input amplifiers feature true differential inputs, a -0.5dB analog bandwidth of 55MHz, and userprogrammable input full-scale ranges of 125mVp-p, 250mVp-p, or 500mVp-p. With an AC-coupled input signal, matching performance between input channels is typically better than 0.1dB gain, 1/4LSB offset, and 0.5° phase. Dynamic performance is 5.85 effective number of bits (ENOB) with a 20MHz analog input signal, or 5.7 ENOB with a 50MHz signal. The MAX1003 operates with +5V analog and +3.3V digital supplies for easy interfacing to +3.3V-logic-compatible digital signal processors and microprocessors. It comes in a 36-pin SSOP package. MAX1003 Low-Power, 90Msps, Dual 6-Bit ADC ABSOLUTE MAXIMUM RATINGS VCC to GND ............................................................-0.3V to 6.5V VCCO to OGND ........................................................-0.3V to 6.5V GND to OGND ........................................................-0.3V to 0.3V Digital and Clock Output Pins to OGND...-0.3V to VCCO (10sec) All Other Pins to GND...............................................-0.3V to VCC Continuous Power Dissipation (TA = +70°C) SSOP (derate 11.8mW/°C above +70°C) ...................941mW Operating Temperature Range...............................0°C to +70°C Storage Temperature Range .............................-65°C to +150°C Lead Temperature (soldering, <10sec)...........................+300°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. DC ELECTRICAL CHARACTERISTICS (VCC = +5V ±5%, VCCO = 3.3V ±300mV, TA = TMIN to TMAX, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS DC ACCURACY (Note 1) Resolution RES 6 Integral Nonlinearity INL -0.5 ±0.25 0.5 LSB Bits Differential Nonlinearity DNL No missing codes over temperature -0.5 ±0.25 0.5 LSB VFSH GAIN = VCC (high gain) 118.75 125 131.25 Full-Scale Input Range VFSM GAIN = open (mid gain) 237.5 250 262.5 VFSL GAIN = GND (low gain) 475 500 525 mVp-p INVERTING AND NONINVERTING ANALOG INPUTS Input Open-Circuit Voltage VAOC 2.25 2.35 2.45 V Input Resistance RIN 13 20 29 kΩ Input Capacitance CIN Guaranteed by design 3 5 pF Common-Mode Voltage Range VCM Other analog input driven with external source (Note 2) 1.75 2.75 V ROSC Other oscillator input tied to VCC + 0.3V 4.8 12.1 kΩ OSCILLATOR INPUTS Oscillator Input Resistance 8 DIGITAL OUTPUTS (DI0–DI5, DQ0–DQ5) Digital Outputs Logic-High Voltage VOH ISOURCE = 50µA Digital Outputs Logic-Low Voltage VOL ISINK = 400µA 0.7VCCO V 0.5 V 63 104 mA -75 -40 dB 21 mA POWER SUPPLY Supply Current Power-Supply Rejection Ratio Digital Outputs Supply Current Power Dissipation 2 ICC PSRR VCC = 4.75V to 5.25V (Note 3) ICCO 20MHz, full-scale I and Q analog inputs, CL = 15pF (Note 4) PD 350 _______________________________________________________________________________________ mW Low-Power, 90Msps, Dual 6-Bit ADC (VCC = +5V ±5%, VCCO = 3.3V ±300mV, TA = +25°C, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS DYNAMIC PERFORMANCE (Gain = open, external 90MHz clock (Figure 7), VINI = VINQ = 20MHz sine, amplitude -1dB below full scale, unless otherwise noted.) Maximum Sample Rate fMAX Analog Input -0.5dB Bandwidth BW 90 GAIN = GND, open, VCC GAIN = open (mid gain) 5.7 ENOBH ENOBL GAIN = VCC (high gain) GAIN = GND (low gain) 5.8 5.85 SINAD GAIN = open (mid gain) 35.5 I channel -0.5 0.5 Q channel -0.5 0.5 OFF Crosstalk Between ADCs XTLK Offset Mismatch Between ADCs OMM Phase Match Between ADCs MHz 5.85 GAIN = open (mid gain), fIN = 50MHz, -1dB below full scale Input Offset (Note 5) Amplitude Match Between ADCs 5.6 ENOBM Effective Number of Bits Signal-to-Noise plus Distortion Ratio Msps 55 Bits 37 dB -55 (Note 5) LSB dB -0.5 ±0.25 0.5 LSB AM -0.2 ±0.1 0.2 dB PM -2 ±0.5 2 degrees TIMING CHARACTERISTICS (Data outputs: RL = 1MΩ, CL = 15pF) Clock to Data Propagation Delay tPD (Note 6) 3.6 ns Data Valid Skew tSKEW (Note 6) 1.5 ns Input to DCLK Delay tDCLK TNK+ to DCLK (Note 6) 5.3 ns Aperture Delay tAD Figure 8 7.5 ns Pipeline Delay PD Figure 8 1 clock cycle Note 1: Best-fit straight-line linearity method. Note 2: A typical application will AC couple the analog input to the DC bias level present at the analog inputs (typically 2.35V). However, it is also possible to DC couple the analog input (using differential or single-ended drive) within this commonmode input range (Figures 4 and 5). Note 3: PSRR is defined as the change in the mid-gain full-scale range as a function of the variation in VCC supply voltage, expressed in decibels. Note 4: The current in the VCCO supply is a strong function of the capacitive loading on the digital outputs. To minimize supply transients and achieve optimal dynamic performance, reduce the capacitive-loading effects by keeping line lengths on the digital outputs to a minimum. Note 5: Offset-correction compensation enabled, 0.22µF at Q and I compensation inputs (Figures 2 and 3). Note 6: tPD and tSKEW are measured from the 1.4V level of the output clock, to the 1.4V level of either the rising or falling edge of a data bit. tDCLK is measured from the 50% level of the clock-overdrive signal on TNK+ to the 1.4V level of DCLK. The capacitive load on the outputs is 15pF. _______________________________________________________________________________________ 3 MAX1003 AC ELECTRICAL CHARACTERISTICS __________________________________________Typical Operating Characteristics (VCC = +5V ±5%, VCCO = 3.3V ±300mV, fCLK = 90Msps, GAIN = open (midgain) MAX1003 evaluation kit, TA = +25°C, unless otherwise noted.) EFFECTIVE NUMBER OF BITS vs. ANALOG INPUT FREQUENCY EFFECTIVE NUMBER OF BITS vs. SAMPLING/CLOCK FREQUENCY ANALOG INPUT BANDWIDTH EFFECTIVE NUMBER OF BITS MAGNITUDE (dB) -0.2 5.4 5.2 -0.4 -0.6 MAX1003-03 0 5.8 5.6 6.0 MAX1003-02 MAX1003-01 6.0 5.9 5.8 5.7 -0.8 5.6 -1.0 5.5 fCLK = 90Msps fIN = 20MHz 5.0 100 10 1 ANALOG INPUT FREQUENCY (MHz) 10 1 100 OSCILLATOR OPEN-LOOP PHASE NOISE vs. FREQUENCY OFFSET 100 FFT PLOT 0 MAX1003-04 -50 fIN = 19.9512MHz fCLK = 90.000MHz 1024 POINTS AC COUPLED SINGLE ENDED AVERAGED AMPLITUDE (dB) -70 PHASE NOISE (dBc) 10 CLOCK FREQUENCY (MHz) ANALOG INPUT FREQUENCY (MHz) -90 -110 MAX1003-05 EFFECTIVE NUMBER OF BITS -20 -40 -130 -60 10k 1k 100k 1M 0 18 27 36 FREQUENCY (MHz) INTEGRAL NONLINEARITY vs. CODE DIFFERENTIAL NONLINEARITY vs. CODE 45 MAX1003-07 MAX1003-06 0.50 0.25 DNL (LSB) 0.25 0 0 -0.25 -0.25 -0.50 -0.50 0 10 20 30 CODE 4 9 FREQUENCY OFFSET FROM CARRIER (Hz) 0.50 INL (LSB) MAX1003 Low-Power, 90Msps, Dual 6-Bit ADC 40 50 60 64 0 10 20 30 40 CODE _______________________________________________________________________________________ 50 60 64 Low-Power, 90Msps, Dual 6-Bit ADC PIN NAME 1 GAIN FUNCTION 2 IOCC+ Positive I-Channel Offset-Correction Compensation. Connect a 0.22µF capacitor for AC-coupled inputs. Ground for DC-coupled inputs. 3 IOCC- Negative I-Channel Offset-Correction Compensation. Connect a 0.22µF capacitor for AC-coupled inputs. Ground for DC-coupled inputs. 4 IIN+ I-Channel Noninverting Analog Input 5 IIN- I-Channel Inverting Analog Input 6 VCC +5V ±5% Supply. Bypass with a 0.01µF capacitor to GND (pin 7). 7, 11, 12, 18, 19 GND Analog Ground 8 VCC +5V ±5% Supply. Bypass with a 0.01µF capacitor to GND (pin 11). 9 TNK+ Positive Oscillator/Clock Input 10 TNK- Negative Oscillator/Clock Input 13 VCC +5V ±5% Supply. Bypass with a 0.01µF capacitor to GND (pin 12). 14 QIN- Q-Channel Inverting Analog Input 15 QIN+ Q-Channel Noninverting Analog Input 16 QOCC- Negative Q-Channel Offset-Correction Compensation. Connect a 0.22µF capacitor for AC-coupled inputs. Ground for DC-coupled inputs. 17 QOCC+ Positive Q-Channel Offset-Correction Compensation. Connect a 0.22µF capacitor for AC-coupled inputs. Ground for DC-coupled inputs. Gain-Select Input. Sets input full-scale range: 125/250/500mVp-p (Table 1). 20–25 DQ5–DQ0 26, 28 VCCO Q-Channel Digital Outputs 0–5. DQ5 is the most significant bit (MSB). Digital Output Supply, +3.3V ±300mV. Bypass each with a 47pF capacitor to OGND (pin 27). 27 OGND Digital Output Ground Digital Clock Output. Frames the output data. 29 DCLK 30–35 DI0–DI5 I-Channel Digital Outputs 0–5. DI5 is the most significant bit (MSB). 36 VCC +5V ±5% Supply. Bypass with a 0.01µF capacitor to GND (pin 19). _______________Detailed Description Converter Operation The MAX1003 contains two 6-bit analog-to-digital converters (ADCs), a buffered voltage reference, and oscillator circuitry. The ADCs use a flash conversion technique to convert an analog input signal into a 6-bit parallel digital output code. The MAX1003’s unique design includes 63 fully differential comparators and a proprietary encoding scheme that ensures no more than 1LSB dynamic encoding error. The control logic interfaces easily to most digital signal processors (DSPs) and microprocessors (µPs) with +3.3V CMOScompatible logic interfaces. Figure 1 shows the MAX1003 in a typical application. Programmable Input Amplifiers The MAX1003 has two (I and Q) programmable-gain input amplifiers with a -0.5dB bandwidth of 55MHz and true differential inputs. To maximize performance in high-speed systems, each amplifier has less than 5pF of input capacitance. The input amplifier gain is programmed, via the GAIN pin, to provide three possible input full-scale ranges (FSRs) as shown in Table 1. Table 1. Input Amplifier Programming GAIN INPUT FULL-SCALE RANGE (mVp-p) GND 500 Open 250 VCC 125 _______________________________________________________________________________________ 5 MAX1003 ______________________________________________________________Pin Description MAX1003 Low-Power, 90Msps, Dual 6-Bit ADC Single-ended and differential AC-coupled input circuits are shown in Figures 2 and 3. Each of the amplifier inputs is internally biased to a 2.35V reference through a 20kΩ resistor, eliminating external DC bias circuits. A series 0.1µF capacitor is required at each amplifier input for AC-coupled signals. When operating with AC-coupled inputs, the input amplifiers’ DC offset voltage is nulled to within ±1/2LSB by an on-chip offset-correction amplifier. An external compensation capacitor is required to set the dominant pole of the offset-correction amplifier’s frequency response (Figures 2 and 3). The compensation capacitor will determine the low-frequency corner of the analog input response according to the following formula: fc = 1 / (0.1 x C) where C is the value of the compensation capacitor in µF, and fc is the corner frequency in Hz. LNB 75Ω CABLE 950MHz TO 2150MHz F-CONNECTOR INPUT KU BAND OR VARACTOR-TUNED PRESELECTION FILTER FROM TANK VOLTAGE VCC AGC AGC RFIN 6 BITS IOUT RFIN 0 90Msps 90 IIN CLK IN MAX2102 DSP 6 BITS EXTERNAL VCO DATA BUFFER QOUT DATA BUFFER QIN LO DIV ADC CLOCK LO MAX1003 TANK SYNTHESIZER MODCTL OR MOD GND TANK TSA5055 or EQUIV. Figure 1. Commercial Satellite Receiver System 6 _______________________________________________________________________________________ FIN CAR Low-Power, 90Msps, Dual 6-Bit ADC _OCC+ _OCC+ _OCC- 0.1µF _IN+ INPUT AMP VSOURCE _IN+ INPUT AMP VSOURCE _IN- _IN- 0.1µF 0.1µF 20k MAX1003 20k 20k 2.35V INTERNAL REFERENCE Figure 3. Differential AC-Coupled Input Figure 2. Single-Ended AC-Coupled Input OFFSET CORRECTION DISABLED _OCC+ MAX1003 20k 2.35V INTERNAL REFERENCE OFFSET CORRECTION DISABLED _OCC- _OCC+ OFFSET CORRECTION _IN+ INPUT AMP VSOURCE INPUT AMP VSOURCE _IN- VREF 1.75V TO 2.75V _OCCOFFSET CORRECTION _IN+ 20k _OCCOFFSET CORRECTION OFFSET CORRECTION 0.1µF MAX1003 0.22µF 0.22µF _IN- MAX1003 20k 2.35V INTERNAL REFERENCE Figure 4. Single-Ended DC-Coupled Input For applications where a DC component of the input signal is present, Figures 4 and 5 show single-ended and differential DC-coupled input circuits. The amplifiers’ input common-mode voltage range extends from 1.75V to 2.75V. To prevent attenuation of the input signal’s DC component in this mode, disable the offsetcorrection amplifier by grounding the _OCC+ and _OCC- pins for the I and Q blocks (Figures 4 and 5). 20k DIFFERENTIAL SOURCE WITH COMMON MODE FROM 1.75V TO 2.75V. MAX1003 20k 2.35V INTERNAL REFERENCE Figure 5. Differential DC-Coupled Input ADCs The I and Q ADC blocks receive the analog signals from the respective I and Q input amplifiers. The ADCs use flash conversion with 63 fully differential comparators to digitize the analog input signal into a 6-bit output in offset binary format. _______________________________________________________________________________________ 7 MAX1003 Low-Power, 90Msps, Dual 6-Bit ADC The MAX1003 features a proprietary encoding scheme that ensures no more than 1LSB dynamic encoding error. Dynamic encoding errors resulting from metastable states may occur when the analog input voltage, at the time the sample is taken, falls close to the decision point for any one of the input comparators. The resulting output code for typical converters can be incorrect, including false full- or zero-scale outputs. The MAX1003’s unique design reduces the magnitude of this type of error to 1LSB. Internal Voltage Reference An internal buffered bandgap reference is included on the MAX1003 to drive the ADCs’ reference ladders. The on-chip reference and buffer eliminate any external (high-impedance) connections to the reference ladder, minimizing the potential for noise coupling from external circuitry while ensuring that the voltage reference, input amplifier, and reference ladder track well with variations of temperature and power supplies. Oscillator Circuit The MAX1003 includes a differential oscillator, which is controlled by an external parallel resonant (tank) network as shown in Figure 6. Alternatively, the oscillator may be overdriven with an external clock source as shown in Figure 7. Internal Clock Operation (Tank) If the tank circuit is used, the resonant inductor should have a sufficiently high Q and a self-resonant frequency (SRF) of at least twice the intended oscillator frequency. Coilcraft’s 1008HS-221, with an SRF of 700MHz and a Q of 45, works well for this application. Generate different clock frequency ranges by adjusting varactor and tank elements. An internal clock-driver buffer is included to provide sharp clock edges to the internal flash comparators. The buffer ensures that the comparators are simultaneously clocked, maximizing the ADCs’ effective number of bits (ENOB) performance. 47k VCLK = 300mVp-p TO 1.25Vp-p 47pF TNK+ 10k 5pF VTUNE TNK+ VCLK TNK- 47pF Z0 = 50Ω CLK DRIVER 220nH 0.1µF 50Ω MAX1003 47k 50Ω CLK DRIVER TNK0.1µF MAX1003 50Ω VTUNE = 0V TO 8V fOSC = 70MHz TO 110MHz VARACTOR DIODE PAIR IS M/A-COM MA4ST079CK-287 (SOT23 PACKAGE) INDUCTOR COILCRAFT 1008HS-221. Figure 6. Tank Resonator Oscillator 8 Figure 7. External Clock Drive Circuit _______________________________________________________________________________________ Low-Power, 90Msps, Dual 6-Bit ADC MAX1003 N N+1 ANALOG INPUT N+2 tAD 50% TNK+ (INPUT CLOCK) tDCLK 1.4V tPD DCLK tSKEW DATA OUT DATA VALID N - 1 1.4V DATA VALID N Figure 8. MAX1003 Timing Diagram Output Data Format The conversion results are output on a dual, 6-bit-wide data bus. Data is latched into the ADC output latch following a pipeline delay of one clock cycle, as shown in Figure 8. Output data is clocked out of the respective ADC’s data output pins (D_0 through D_5) on the rising edge of the clock output (DCLK), with a DCLK-to-data propagation delay (tPD) of 3.6ns. The MAX1003 outputs are +3.3V CMOS-logic compatible. Transfer Function Figure 9 shows the MAX1003’s nominal transfer function. Output coding is offset binary with 1LSB = FSR / 63. 111111 111110 111101 OUTPUT CODE External Clock Operation To accommodate designs that use an external clock, the MAX1003’s internal oscillator can be overdriven by an external clock source as shown in Figure 7. The external clock source should be a sinusoid to minimize clock phase noise and jitter, which can degrade the ADCs’ ENOB performance. AC couple the clock source (recommended voltage level is approximately 1Vp-p) to the oscillator inputs as shown in Figure 7. 100001 100000 011111 011110 000011 000010 000001 000000 -FSR 2 0 1LSB INPUT VOLTAGE (_IN+ TO _IN-) FSR 2 Figure 9. Ideal Transfer Function _______________________________________________________________________________________ 9 MAX1003 Low-Power, 90Msps, Dual 6-Bit ADC __________Applications Information _____________Dynamic Performance The MAX1003 is designed with separate analog and digital power-supply and ground connections to isolate high-current digital noise spikes from the more sensitive analog circuitry. The high-current digital output ground (OGND) and analog ground (GND) should be at the same DC level, connected at only one location on the board. This will provide best noise immunity and improved conversion accuracy. Use of separate ground planes is strongly recommended. Signal-to-noise and distortion (SINAD) is the ratio of the fundamental input frequency’s RMS amplitude to all other ADC output signals. The output spectrum is limited to frequencies above DC and below one-half the ADC sample rate. The theoretical minimum analog-to-digital noise is caused by quantization error, and results directly from the ADC’s resolution: SNR = (6.02N + 1.76)dB, where N is the number of bits of resolution. Therefore, a perfect 6-bit ADC can do no better than 38dB. The FFT Plot (see Typical Operating Characteristics) shows the result of sampling a pure 20MHz sinusoid at a 90MHz clock rate. This FFT plot of the output shows the output level in various spectral bands. The plot has been averaged to reduce the quantization noise floor and reveal the low-amplitude spurs. This emphasizes the excellent spurious-free dynamic range of the MAX1003. The effective resolution (or effective number of bits) the ADC provides can be measured by transposing the equation that converts resolution to SINAD: N = (SINAD - 1.76) / 6.02 (see Typical Operating Characteristics). The entire board needs good DC bypassing for both analog and digital supplies. Place the power-supply bypass capacitors close to where the power is routed onto the board, i.e., close to the connector. 10µF electrolytic capacitors with low-ESR ratings are recommended. For best effective bits performance, minimize capacitive loading at the digital outputs. Keep the digital output traces as short as possible. The MAX1003 requires a +5V ±5% power supply for the analog supply (VCC) and a +3.3V ±300mV power supply connected to V CCO for the logic outputs. Bypass each of the VCC_ supply pins to its respective GND with high-quality ceramic capacitors located as close to the package as possible (Table 2). Consult the evaluation kit manual for a suggested layout and bypassing scheme. Table 2. Bypassing 10 SUPPLY FUNCTION VCC/ VCCO BYPASS TO GND/ OGND CAPACITOR VALUE Analog Inputs 6 7 0.01µF Oscillator/Clock 8 11 0.01µF 0.01µF Converter 13 12 Digital Q-Output 26 27 47pF Digital I-Output 28 27 47pF Buffer 36 19 0.01µF ______________________________________________________________________________________ Low-Power, 90Msps, Dual 6-Bit ADC MAX1003 __________________Pin Configuration TOP VIEW GAIN 1 36 VCC IOCC+ 2 35 DI5 IOCC- 3 34 DI4 IIN+ 4 33 DI3 IIN- 5 32 DI2 MAX1003 31 DI1 VCC 6 GND 7 30 DI0 VCC 8 29 DCLK TNK+ 9 28 VCCO TNK- 10 27 OGND GND 11 26 VCCO GND 12 25 DQ0 VCC 13 24 DQ1 QIN- 14 23 DQ2 QIN+ 15 22 DQ3 QOCC- 16 21 DQ4 QOCC+ 17 20 DQ5 GND 18 19 GND SSOP ___________________Chip Information TRANSISTOR COUNT: 6097 ______________________________________________________________________________________ 11 ________________________________________________________Package Information SSOP2.EPS MAX1003 Low-Power, 90Msps, Dual 6-Bit ADC Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 12 __________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 (408) 737-7600 © 1997 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.