MP7683 CMOS 8-Bit High Speed Analog-to-Digital Converter FEATURES APPLICATIONS • • • • • • • • • • 3 MHz Sampling Rate Non-Linearity +1/4 LSB (typ) with S/H Low Power CMOS - 100mW (typ) Requires NO SAMPLE AND HOLD for signals less than 100 kHz • Single Supply Voltage (+4 V to +6 V) • Latch-Up Free High Speed Low Power A/D Conversion Satellite Operations High Energy Physics Research Portable Products Radar Pulse Analysis µP Data Acquisition Systems LSBs and consists of 32 auto-balanced comparators, latches, an encoder, and five buffer storage registers. The MP7683 operates over a wide, full-scale input voltage range from 4.0 volts up to 6.5 volts, full-scale. GENERAL DESCRIPTION The MP7683 is a monolithic CMOS 8-bit two step flash Analog-to-Digital Converter designed for applications which demand Low Power Consumption and High Speed digitization (2 MHz sampling rate, 100mW power dissipation). The linearity error is 1/4 LSB (typical), with clock frequency of 2 MHz at a supply voltage of 5 volts. The overflow bit makes it possible to achieve 9-bit resolution by connecting two MP7683’s in series. See Figure 3. Specified for operation over the commercial / industrial (–40 to +85°C) and military (–55 to +125°C) temperature ranges, the MP7683 is available in Plastic (PDIP) and Ceramic (CDIP) dualin-line, Shrunk Small Outline (SSOP) and Surface Mount (SOIC) packages. The MP7683 conversion is done in two segments. The first segment converts the 3 MSBs and consists of eight (8) auto– balanced comparators, latches, an encoder, and four buffer storage registers. The second segment converts the five (5) SIMPLIFIED BLOCK DIAGRAM VIN AVDD DVDD VREF(+) OFW DB7 (MSB) R4 Comparators Latches Encoder Adders Buffers DB6 DB5 R3 R2 Resistor Ladder and Switches DB4 R1 Comparators Latches Encoder Buffers DB3 DB2 DB1 DB0 (LSB) VREF(–) OE1 OE2 CLK PHASE Rev. 2.00 1 AGND DGND MP7683 ORDERING INFORMATION Temperature Range Part No. DNL (LSB) INL (LSB) Plastic Dip –40 to +85°C MP7683JN 1 1/4 1 1/4 Plastic Dip –40 to +85°C MP7683KN 3/4 –40 to +85°C 3/4 SOIC MP7683JS 1 1/4 SOIC –40 to +85°C 1 1/4 MP7683KS 3/4 –40 to +85°C 3/4 SSOP MP7683JQ 1 1/4 1 1/4 Package Type –40 to +85°C SSOP Ceramic Dip Ceramic Dip –55 to +125°C –55 to +125°C MP7683KQ 3/4 3/4 MP7683SD* 1 1/4 1 1/4 MP7683TD* 3/4 3/4 *Contact factory for non-compliant military processing PIN CONFIGURATIONS OE2 PHASE CLK DVDD AVDD VREF(+) VREF(–) R1 R2 R3 R4 VIN 1 24 2 23 3 22 4 21 5 20 6 19 7 18 8 17 9 16 10 15 11 14 12 13 OE2 PHASE CLK DVDD AVDD VREF(+) VREF(–) R1 R2 R3 R4 OE1 OFW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DGND AGND VIN 24 Pin CDIP, PDIP (0.600”) D24, N24 1 24 2 23 3 22 4 21 5 20 6 19 7 18 8 17 9 16 10 15 11 14 12 13 OE1 OFW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DGND AGND 24 Pin SOIC (EIAJ, 0.335”) - R24 24 Pin SSOP - A24 PIN OUT DEFINITIONS PIN NO. NAME DESCRIPTION PIN NO. NAME DESCRIPTION 1 OE2 Output Enable Control 2 13 AGND Analog Ground 2 PHASE Sampling Clock Phase Control 14 DGND Digital Ground 3 CLK Clock Input 15 DB0 Data Output Bit 0 (LSB) 4 DVDD Power Supply 16 DB1 Data Output Bit 1 5 AVDD Power Supply for Analog Circuit 17 DB2 Data Output Bit 2 6 VREF(+) Reference Voltage (+) Input 18 DB3 Data Output Bit 3 7 VREF(–) Reference Voltage (–) Input 19 DB4 Data Output Bit 4 8 R1 1/16th Point of Ladder R Matrix 20 DB5 Data Output Bit 5 9 R2 5/16th Point of Ladder R Matrix 21 DB6 Data Output Bit 6 10 R3 9/16th Point of Ladder R Matrix 22 DB7 Data Output Bit 7 (MSB) 11 R4 13/16th Point of Ladder R Matrix 23 OFW Digital Output Overflow 12 VIN Analog Input 24 OE1 Output Enable Control 1 Rev. 2.00 2 MP7683 ELECTRICAL CHARACTERISTICS TABLE Unless Otherwise Specified: AVDD = DVDD = 5 V, FS = 3 MHz (50% Duty Cycle), VREF(+) = 4.1, VREF(–) = AGND, TA = 25°C Parameter Symbol Min FS 8 0.001 25°C Typ Max Tmin to Tmax Min Max Units 8 0.001 3 Bits MHz Test Conditions/Comments KEY FEATURES Resolution Sampling Rate 3 For specified accuracy ACCURACY (J, S Grades)1 Differential Non-Linearity Integral Non-Linearity DNL INL +1 1 +1 1/4 1 1/4 LSB LSB DNL INL +1/2 1/2 +3/4 3/4 LSB LSB AVDD 2 AVDD AGND 4.1 AVDD-AGND 300 1950 2000 Best Fit Line (Max INL – Min INL) / 2 ACCURACY (K, T Grades)1 Differential Non-Linearity Integral Non-Linearity Best Fit Line REFERENCE VOLTAGES Positive Ref. Voltage Negative Ref. Voltage Differential Ref. Voltage2 Ladder Resistance Ladder Temp. Coefficient2 VREF(+) VREF(–) VREF RL RTCO 2 AGND 4.1 500 4.1 AVDD-AGND 1500 V V V Ω ppm/°C For specified accuracy ANALOG INPUT Input Voltage Range Input Impedance2 Input Capacitance4 Aperture Delay2 Aperture Uncertainty (Jitter)2 VIN VREF(–) ZIN CINA tAP tAJ VREF(+) VREF(–) VREF(+) 10 50 55 200 V p-p MΩ pF ns ps DIGITAL INPUTS Logical “1” Voltage Logical “0” Voltage Leakage Currents5 CLK Input Capacitance2 Clock Timing (See Figure 1.) Clock Period “High” Time “Low” Time Duty Cycle VIH VIL 3.5 3.5 tS th tl 1.5 +50 +50 V V 5 µA pF 50 ns ns ns % IIN CIND 1.5 333 166.5 166.5 Rev. 2.00 3 VIN = DGND to DVDD MP7683 ELECTRICAL CHARACTERISTICS TABLE CONT’D Parameter Symbol Min 25°C Typ Max Tmin to Tmax Min Max Units COUT=15 pF DIGITAL OUTPUTS Logical “1” Voltage Logical “0” Voltage Tristate Leakage Data Valid Delay2 Data Enable Delay2 Data Tristate Delay2 Output Capacitance2 Test Conditions/Comments VOH VOL IOZ tDL tDEN tDHZ CO 4.6 VDD6 IDD 4 4.6 0.4 +50 0.4 +50 55 20 26 5 V V µA ns ns ns pF ILOAD = –1.0 mA ILOAD = 2.0 mA VOUT=DGND to DVDD (See Figure 1.) (See Figure 2.) (See Figure 2.) POWER SUPPLIES Operating Voltage (AVDD, DVDD) Current (AVDD + DVDD) 6.5 20 4 6.5 36 V mA NOTES 1 Tester measures code transitions by dithering the voltage of the analog input (VIN). The difference between the measured and the ideal code width (VREF/256) is the DNL error. The INL error is the maximum distance (in LSB) from the best fit line to any transition voltage. Accuracy is a function of the sampling rate (FS). 2 Guaranteed. Not tested. 3 Specified values guarantee functionality. Refer to other parameters for accuracy. 4 See VIN input equivalent circuit (Figure 4). Switched capacitor analog input requires driver with low output resistance. 5 All inputs have diodes to DVDD and DGND. 6 DVDD and AVDD are connected through the silicon substrate. Connect together at the package and to the analog supply loop. Specifications are subject to change without notice ABSOLUTE MAXIMUM RATINGS (TA = +25°C unless otherwise noted)1, 2, 3 Lead Temperature (Soldering 10 seconds) . . . . . . . +300°C Package Power Dissipation Rating to 75°C CDIP, PDIP, SOIC . . . . . . . . . . . . . . . . . . . . . . . . 1000mW Derates above 75°C . . . . . . . . . . . . . . . . . . . . . 14mW/°C SSOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 750mW Derates above 75°C . . . . . . . . . . . . . . . . . . . . . 10mW/°C VDD (to GND) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +6.5 V VREF(+) & VREF(–) . . . . . . . . . . . . . . GND –0.5 to VDD +0.5 V VIN . . . . . . . . . . . . . . . . . . . . . . . . . . GND –0.5 to VDD +0.5 V Digital Inputs . . . . . . . . . . . . . . . . . . GND –0.5 to VDD +0.5 V Digital Outputs . . . . . . . . . . . . . . . . GND –0.5 to VDD +0.5 V Storage Temperature . . . . . . . . . . . . . . . . . –65°C to +150°C NOTES: 1 Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation at or above this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. 2 Any input pin which can see a value outside the absolute maximum ratings should be protected by Schottky diode clamps (HP5082-2835) from input pin to the supplies. All inputs have protection diodes which will protect the device from short transients outside the supplies of less than 100mA for less than 100µs. 3 VDD refers to AVDD and DVDD. GND refers to AGND and DGND. Rev. 2.00 4 MP7683 the data is valid for every clock period. The OE1 will independently disable DB0 through DB7 when it is in a high state. CE2 will independently disable DB0 through DB7 and the OFW buffers when it is in a low state. The Truth Table (Table 1.) summarizes this effect. DEVICE OPERATION Figure 1. shows the timing diagram of the MP7683 8-bit Flash Converter. A reference voltage is applied between the VREF(+) and VREF(–) which drives 256 resistors and switches with 4 voltage taps. These taps drive the inverting inputs of comparators. There are four control lines: Clock, OE1 , OE2, and Phase. The phase line determines the polarity of the clock. OE1 OE2 DB7-DB0 OFW 0 1 X 1 1 0 Valid Tri-State Tri-State Valid Valid Tri-State Figure 2. shows waveforms with the phase line high and low. With 0 = 1, the “sample” occurs during the high period of the clock cycle and the “auto-balance” occurs during the low period of the clock. The “sample” is queued and pipelined through a series of registers and latches. It appears at the output after 2 clock periods and time delay (Td). After the sample is acquired th Table 1. Truth Table tl PHASE = 0 1 CLK 0 Sample 1 Sample 2 TS Sample 3 Sample 4 tDL DB7-DB0 OFW Data Valid Sample 1 PHASE = 1 1 CLK 0 Sample 1 Sample 2 Sample 3 Data Valid Sample 2 Sample 4 tDL DB7-DB0 OFW Data Valid Sample 1 Data Valid Sample 2 Figure 1. Timing Diagram OE1 OE2 DB7-DB0 OFW tDIS (26 ns typ) tEN (20 ns typ) DATA tDIS DATA DATA tEN HIGH IMPEDANCE DATA HIGH IMPEDANCE DATA Figure 2. Output Enable and Disable Timing Diagram Rev. 2.00 5 MP7683 VREF OE2 OE1 PHASE OFW OFW 09 08 07 06 05 04 03 02 01 DB7 CLK DVDD AVDD CLK +5V VREF(+) VREF(–) R1 R2 R3 R4 M P 7 6 8 3 DB0 Data Output DGND AGND VIN OE1 OE2 VDD PHASE OFW DB7 CLK DVDD AVDD +5V VREF(+) VREF(–) R1 R2 R3 R4 M P 7 6 8 3 DB0 DGND AGND Analog Input VIN Figure 3. MP7683 9-Bit Resolution Configuration OE2 CLK +5 V 0.1µF +5 V 0.1µF VREF(+) 0.1µF 0.1µF 0.1µF 0.1µF Analog Input 0.1µF OE1 PHASE OFW CLK DB7 DVDD DB6 AVDD VREF(+) VREF(–) M P 7 6 8 3 DB5 DB3 DB2 R2 DB1 R3 DB0 R4 DGND VIN AGND Figure 4. MP7683 Typical Connections 6 SIGNAL OUTPUT DB4 R1 Rev. 2.00 OFW DB7 DB0 Analog GND MP7683 6. APPLICATION NOTES: The following information will be useful in maximizing the performance of the MP7683. The power supplies and reference voltages should be decoupled with ceramic (0.01 to 0.1µF) and tantalum (10µF) capacitors as close to the device as possible. 7. The digital output should not drive long wires. The capacitive coupling and reflection will contribute noise to the conversion. When driving distant loads, buffers should be used. 1. This device may be susceptible to latch-up. All signals must not exceed AVDD or AGND, or DVDD or DGND at any time. Digital Supply (DVDD & AVDD) must be applied before all other signals to avoid a latch-up condition. 2. The design of a PC layout and assembly will seriously affect the accuracy of the MP7683. Use of wire wrap is not recommended. 3. The analog input signal (VIN) is quite sensitive and should be properly routed and terminated. It should be shielded from the clock and digital outputs so as to minimize cross coupling and noise pickup. φ2 No Max 5µs max 5. The use of a large shield plane is highly recommended, connected only at one point and connected to virtual ground. The ground plane should act as a shield for parasitics and not a return path for signals. To reduce noise levels, use separate low impedance ground paths. 40 pF φS 15 pF 250 Ω VIN AGND φ2 8. To avoid a possible latch-up condition, power should be applied before any input signal is connected. 100 Ω φS 15 pF φ1 a. When at 50% Duty Cycle, the minimum clock rate is 100 kHz. b. When at non-50% Duty Cycle, the minimum clock rate may be DC as long as 2 is kept to less than 5 µs. 4. The analog input should be driven with a buffer op amp (ZOUT < 50 Ω). AVDD φ1 φB 600 Ω 3 pF 1/2 [ VREF(+) + VREF(–) ] Figure 5. Analog Input Equivalent Circuit Rev. 2.00 7 MP7683 PERFORMANCE CHARACTERISTICS Graph 1. Supply Current vs. Sampling Frequency Graph 2. DNL vs. Sampling Frequency Graph 3. INL vs. Sampling Frequency Graph 4. DNL vs. Reference Voltage Graph 5. INL vs. Reference Voltage Graph 6. Supply Current vs. Temperature Rev. 2.00 8 MP7683 Graph 7. Reference Resistance vs. Temperature Graph 8. DNL vs. Temperature Graph 9. INL vs. Temperature Graph 10. Output Delay vs. Supply Voltage Graph 11. Data Hold Time vs. Supply Voltage Graph 12. Aperture Delay vs. Supply Voltage Rev. 2.00 9 MP7683 Graph 13. Tristate Enable Delay vs. Supply Voltage Graph 14. DNL Error Plot Graph 15. INL Error Plot Rev. 2.00 10 MP7683 24 LEAD CERAMIC DUAL-IN-LINE (600 MIL CDIP) D24 S S1 24 13 1 12 See Note 1 E1 E D Q Base Plane Seating Plane A L c e b L1 b α 1 INCHES SYMBOL A NOTES MILLIMETERS MIN MAX MIN MAX –– 0.225 –– 5.72 NOTES –– b 0.014 0.023 0.356 0.584 –– b1 0.038 0.065 0.965 1.65 2 c 0.008 0.015 0.203 0.381 –– D –– 1.290 –– 32.77 4 E 0.500 0.610 12.70 15.49 4 E1 0.590 0.620 14.99 15.75 7 e 0.100 BSC 2.54 BSC 5 L 0.120 0.200 3.05 5.08 –– L1 0.150 –– 3.81 –– –– Q 0.015 0.075 0.381 1.91 3 S –– 0.098 –– 2.49 6 0.005 –– 0.13 –– 6 0° 15° 0° 15° –– S1 α Rev. 2.00 11 1. Index area; a notch or a lead one identification mark is located adjacent to lead one and is within the shaded area shown. 2. The minimum limit for dimension b1 may be 0.023 (0.58 mm) for all four corner leads only. 3. Dimension Q shall be measured from the seating plane to the base plane. 4. This dimension allows for off-center lid, meniscus and glass overrun. 5. The basic lead spacing is 0.100 inch (2.54 mm) between centerlines. 6. Applies to all four corners. 7. This is measured to outside of lead, not center. MP7683 24 LEAD PLASTIC DUAL-IN-LINE (600 MIL PDIP) N24 S 24 13 E1 1 12 Q1 E D A1 Seating Plane A L B e B1 α MILLIMETERS INCHES SYMBOL A MIN MAX MIN –– 0.225 –– MAX 5.72 A1 0.015 –– 0.38 –– B 0.014 0.023 0.356 0.584 B1 (1) 0.038 0.065 0.965 1.65 C 0.008 0.015 0.203 0.381 D 1.160 1.290 29.46 32.77 E 0.585 0.625 14.86 15.88 E1 0.500 0.610 12.70 15.49 e 0.100 BSC 2.54 BSC L 0.115 0.150 2.92 3.81 α 0° 15° 0° 15° Q1 0.055 0.070 1.40 1.78 S 0.040 0.098 1.02 2.49 Note: (1) The minimum limit for dimensions B1 may be 0.023” (0.58 mm) for all four corner leads only. Rev. 2.00 12 C MP7683 24 LEAD SMALL OUTLINE (335 MIL EIAJ SOIC) R24 D 24 13 E 1 H 12 C A Seating Plane e B A1 L MILLIMETERS SYMBOL A A1 MIN 2.60 INCHES MAX MIN 2.80 0.102 0.2 (typ.) MAX 0.110 0.008 (typ.) B 0.3 0.50 .012 0.020 C 0.10 0.20 0.004 0.008 D 15.0 15.4 0.590 0.606 E 8.3 8.5 0.327 0.335 e 1.27 (typ.) 0.050 (typ.) H 11.5 12.1 0.453 0.477 L 0.8 1.2 0.031 0.047 Rev. 2.00 13 MP7683 24 LEAD SHRINK SMALL OUTLINE PACKAGE (SSOP) A24 D 24 13 E 1 H 12 C A Seating Plane α B e A1 L MILLIMETERS SYMBOL INCHES MIN MAX MIN A 1.73 2.05 0.068 0.081 A1 0.05 0.21 0.002 0.008 B 0.20 0.40 0.008 0.016 C 0.13 0.25 0.005 0.010 D 8.07 8.40 0.318 0.331 E 5.20 5.38 0.205 0.212 e 0.65 BSC MAX 0.0256 BSC H 7.65 8.1 0.301 0.319 L 0.45 0.95 0.018 0.037 α 0° 8° 0° 8° Rev. 2.00 14 MP7683 Notes Rev. 2.00 15 MP7683 NOTICE EXAR Corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contains here in are only for illustration purposes and may vary depending upon a user’s specific application. While the information in this publication has been carefully checked; no responsibility, however, is assumed for inaccuracies. EXAR Corporation does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corporation is adequately protected under the circumstances. Copyright EXAR Corporation Datasheet April 1995 Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited. Rev. 2.00 16