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INTEGRATED CIRCUITS

Jameco Part Number 310113

74ALS74A
Dual D-type flip-flop with set and reset
Product specification
IC05 Data Handbook


 
 

 

1996 Jul 01

Philips Semiconductors

Product specification

Dual D-type flip-flop with set and reset

DESCRIPTION

ORDERING INFORMATION

The 74ALS74 is a dual positive edge-triggered D-type flip-flop
featuring individual data, clock, set, and reset inputs; also true and
complementary outputs. Set (SD) and reset (RD) are asynchronous
active-Low inputs and operate independently of the clock input.
When set and reset are inactive (High), data at the D input is
transferred to the Q and Q outputs on the Low-to-High transition of
the clock. Data must be stable just one setup time prior to the
Low-to-High transition of the clock for predictable operation. Clock
triggering occurs at a voltage level and is not directly related to the
transition time of the positive-going pulse. Following the hold time
interval, data at the D input may be changed without affecting the
levels of the output.

TYPE

74ALS74A

TYPICAL fMAX

TYPICAL
SUPPLY CURRENT
(TOTAL)

150MHz

3.0mA

74ALS74A

ORDER CODE
DESCRIPTION

COMMERCIAL RANGE
VCC = 5V ±10%,
Tamb = 0°C to +70°C

DRAWING
NUMBER

14-pin plastic DIP

74ALS74AN

SOT27-1

14-pin plastic SO

74ALS74AD

SOT108-1

14-pin plastic SSOP
Type II

74ALS74ADB

SOT337-1

PIN CONFIGURATION
RD0

1

14

VCC

D0

2

13

RD1

CP0

3

12

D1

SD0

4

11

CP1

Q0

5

10

SD1

Q0

6

9

Q1

GND

7

8

Q1

SF00045

INPUT AND OUTPUT LOADING AND FAN-OUT TABLE
74ALS (U.L.)
HIGH/LOW

LOAD VALUE
HIGH/LOW

Data inputs

1.0/2.0

20µA/0.2mA

CP0, CP1

Clock inputs (active rising edge)

1.0/2.0

20µA/0.2mA

SD0, SD1

Set inputs (active-Low)

2.0/4.0

40µA/0.4mA

RD0, RD1

Reset inputs (active-Low)

2.0/4.0

40µA/0.4mA

Data outputs

20/80

0.4mA/8mA

PINS

DESCRIPTION

D0, D1

Q0, Q1, Q0, Q1

NOTE: One (1.0) ALS unit load is defined as: 20µA in the High state and 0.1mA in the Low state.

LOGIC SYMBOL

IEC/IEEE SYMBOL
2

12
4

D0 D1
3

CP0

4

SD0

1

RD0

2
1

11

CP1

10

SD1

13

RD1

10

5

1D

6

R

S

9

11
C2
12
13
6

9

2D

8

R

8

SF00047

SF00046

1996 Jul 01

5
C1

Q0 Q0 Q1 Q1

VCC = Pin 14
GND = Pin 7

&

S

3

2

853–1278 01670

Philips Semiconductors

Product specification

Dual D-type flip-flop with set and reset

74ALS74A

LOGIC DIAGRAM

FUNCTION TABLE
INPUTS

SD

RD

CP

D

4, 10

5, 9

1, 13

Q

6, 8

3, 11

Q

OUTPUTS

OPERATING

SD

RD

CP

D

Q

Q

L

H

X

X

H

L

Asynchronous set

MODE

H

L

X

X

L

H

Asynchronous reset

L

L

X

X

H

H

Undetermined*

H

H

↑

h

H

L

Load “1”

H

H

↑

l

L

H

Load “0”

H

H

↑

X

NC

NC

Hold

H = High voltage level
h = High state must be present one setup time prior to
Low-to-High clock transition
L = Low voltage level
l = Low state must be present one setup time prior to
Low-to-High clock transition
NC= No change from the previous setup
X = Don’t care
↑ = Low-to-High clock transition
↑ = Not Low-to-High clock transition
* = Both outputs will be High while both SD and RD are Low,
but the output states are unpredictable if SD and RD go
High simultaneously

2, 12

VCC = Pin 14
GND = Pin 7

SF00048

ABSOLUTE MAXIMUM RATINGS
(Operation beyond the limit set forth in this table may impair the useful life of the device.
Unless otherwise noted these limits are over the operating free-air temperature range.)
SYMBOL

PARAMETER

RATING

UNIT

VCC

Supply voltage

–0.5 to +7.0

V

VIN

Input voltage

–0.5 to +7.0

V

IIN

Input current

–30 to +5

mA

–0.5 to VCC

V

VOUT

Voltage applied to output in High output state

IOUT

Current applied to output in Low output state

Tamb

Operating free-air temperature range

Tstg

Storage temperature range

16

mA

0 to +70

°C

–65 to +150

°C

RECOMMENDED OPERATING CONDITIONS
LIMITS
SYMBOL

PARAMETER

UNIT
MIN

NOM

MAX

5.0

5.5

VCC

Supply voltage

4.5

VIH

High-level input voltage

2.0

VIL

Low-level input voltage

0.8

V

IIk

Input clamp current

–18

mA

IOH

High-level output current

–0.4

mA

IOL

Low-level output current

8

mA

+70

°C

Tamb

1996 Jul 01

Operating free-air temperature range

0

3

V
V

Philips Semiconductors

Product specification

Dual D-type flip-flop with set and reset

74ALS74A

DC ELECTRICAL CHARACTERISTICS
(Over recommended operating free-air temperature range unless otherwise noted.)
SYMBOL

LIMITS

TEST CONDITIONS1

PARAMETER

MIN
VOH

High-level output voltage

VCC = ±10%,
VIL = MAX, VIH = MIN

VOL
O

Low level output voltage
Low-level

VCC = MIN,, VIL = MAX,,
VIH = MIN

VIK

Input clamp voltage

IOH = MAX

Input current at maximum input
voltage

IIH

High level input current
High–level

IIL

Low
level input current
Low–level

IO

Output current3

V

IOL = 4mA

0.25

0.40

V

IOL = 8mA

0.35

0.50

V

–0.73

–1.5

V

0.1

mA

0.2

mA

20

µA

40

µA

–0.2

mA

–0.4

mA

–112

mA

4.0

mA

Dn, CPn
SDn, RDn

VCC = MAX,
MAX VI = 7
7.0V
0V

Dn, CPn
SDn, RDn

VCC = MAX,
MAX VI = 2
2.7V
7V

Dn, CPn

ICC

SDn, RDn

Supply current

VCC = MAX,
MAX VI = 0
4V
0.4V
VCC = MAX, VO = 2.25V

(total)4

UNIT
MAX

VCC – 2

VCC = MIN, II = IIK

II

TYP2

–30

VCC = MAX

3.0

NOTES:
1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type.
2. All typical values are at VCC = 5V, Tamb = 25°C.
3. The output conditions have been chosen to produce a current that closely approximates one half of the true short–circuit output current, IOS.
4. Measure ICC with the Dn, CPn, and SDn grounded, then with Dn, CPn, and RDn grounded.

AC ELECTRICAL CHARACTERISTICS
LIMITS
SYMBOL

PARAMETER

TEST CONDITION

Tamb = 0°C to +70°C
VCC = +5.0V ± 10%
CL = 50pF, RL = 500Ω
MIN

UNIT

MAX

fmax

Maximum clock frequency

Waveform 1

80

MHz

tPLH
tPHL

Propagation delay
CPn to Qn or Qn

Waveform 1

3.0
3.0

14.0
14.0

ns

tPLH
tPHL

Propagation delay
SDn or RD to Qn or Qn

Waveform 2, 3

1.0
3.0

8.0
10.0

ns

AC SETUP REQUIREMENTS
LIMITS
SYMBOL

PARAMETER

TEST CONDITION

Tamb = 0°C to +70°C
VCC = +5.0V ± 10%
CL = 50pF, RL = 500Ω
MIN

UNIT

MAX

tsu (H)
tsu (L)

Setup time, High or Low
Dn to CPn

Waveform 1

6.0
6.0

ns

th (H)
th (L)

Hold time, High or Low
Dn to CPn

Waveform 1

0.0
0.0

ns

tw (H)
tw (L)

CPn Pulse width
High or Low

Waveform 1

6.0
6.0

ns

tw (L)

SDn or RDn Pulse width, Low

Waveform 2, 3

6.0

ns

Recovery time, SDn or RDn to CPn

Waveform 2, 3

6.0

ns

trec

1996 Jul 01

4

Philips Semiconductors

Product specification

Dual D-type flip-flop with set and reset

74ALS74A

AC WAVEFORMS
For all waveforms, VM = 1.3V.
The shaded areas indicate when the input is permitted to change for predictable output performance.

Dn

VM
tsu(L)

VM

VM
tsu(H)

th(L)

VM
th(H)

1/fmax
CPn

VM

tw(L)

VM

VM

tw(H)

tPHL

tPLH
Qn

VM

VM
tPLH

tPHL

VM

VM

Qn

SF00049

Waveform 1. Propagation Delay for Data to Output,
Data Setup and Hold Times, Clock Width,
and Maximum Clock Frequency

Dn

SDn

Dn

VM

tw(L)

RDn

VM

VM

tw(L)
VM

tREC
CPn

tREC
CPn

VM

tPLH
Qn

tPLH
Qn

VM
tPHL

Qn

VM
tPHL

VM

Qn

SC00040

VM

SC00041

Waveform 2. Propagation Delay for Set to Output,
Set Pulse Width and Recovery Time for Set to Clock

1996 Jul 01

VM

Waveform 3. Propagation Delay for Reset to Output,
Reset Pulse Width and Recovery Time for Reset to Clock

5

Philips Semiconductors

Product specification

Dual D-type flip-flop with set and reset

74ALS74A

TEST CIRCUIT AND WAVEFORMS
VCC
NEGATIVE
PULSE
VIN

CL

RL

AMP (V)

VM

10%

D.U.T.

RT

90%

VM

VOUT

PULSE
GENERATOR

tw

90%

10%

tTHL (tff)

tTLH (tr )

tTLH (tr )

tTHL (tf )

0.3V

AMP (V)
90%

90%

Test Circuit for Totem-pole Outputs

POSITIVE
PULSE

VM

VM
10%

10%

tw

0.3V

Input Pulse Definition

DEFINITIONS:
RL = Load resistor;
see AC electrical characteristics for value.
CL = Load capacitance includes jig and probe capacitance;
see AC electrical characteristics for value.
RT = Termination resistance should be equal to ZOUT of
pulse generators.

INPUT PULSE REQUIREMENTS
Family
Amplitude VM
74ALS

3.5V

1.3V

Rep.Rate

tw

tTLH

tTHL

1MHz

500ns

2.0ns

2.0ns
SC00005

1996 Jul 01

6

Philips Semiconductors

Product specification

Dual D-type flip-flop with set and reset

74ALS74A

DEFINITIONS
Data Sheet Identification

Product Status

Definition

Objective Specification

Formative or in Design

This data sheet contains the design target or goal specifications for product development. Specifications
may change in any manner without notice.

Preliminary Specification

Preproduction Product

This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips
Semiconductors reserves the right to make changes at any time without notice in order to improve design
and supply the best possible product.

Product Specification

Full Production

This data sheet contains Final Specifications. Philips Semiconductors reserves the right to make changes
at any time without notice, in order to improve design and supply the best possible product.

Philips Semiconductors and Philips Electronics North America Corporation reserve the right to make changes, without notice, in the products,
including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips
Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright,
or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask
work right infringement, unless otherwise specified. Applications that are described herein for any of these products are for illustrative purposes
only. Philips Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing
or modification.
LIFE SUPPORT APPLICATIONS
Philips Semiconductors and Philips Electronics North America Corporation Products are not designed for use in life support appliances, devices,
or systems where malfunction of a Philips Semiconductors and Philips Electronics North America Corporation Product can reasonably be expected
to result in a personal injury. Philips Semiconductors and Philips Electronics North America Corporation customers using or selling Philips
Semiconductors and Philips Electronics North America Corporation Products for use in such applications do so at their own risk and agree to fully
indemnify Philips Semiconductors and Philips Electronics North America Corporation for any damages resulting from such improper use or sale.
 Copyright Philips Electronics North America Corporation 1997
All rights reserved. Printed in U.S.A.

Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Sunnyvale, California 94088–3409
Telephone 800-234-7381


 
 
1991 Jul 01

 
7

Philips Semiconductors

Product specification

Dual D-type flip-flop with set and reset

74ALS74A

DIP14: plastic dual in-line package; 14 leads (300 mil)

1996 Jul 01

8

SOT27-1

Philips Semiconductors

Product specification

Dual D-type flip-flop with set and reset

74ALS74A

SO14: plastic small outline package; 14 leads; body width 3.9 mm

1996 Jul 01

9

SOT108-1

Philips Semiconductors

Product specification

Dual D-type flip-flop with set and reset

74ALS74A

NOTES

1996 Jul 01

10