Dual Bootstrapped 12 V MOSFET
Driver with Output Disable
ADP3418
FEATURES
All-In-One Synchronous Buck Driver
Bootstrapped High-Side Drive
1 PWM Signal Generates Both Drives
Anticross-Conduction Protection Circuitry
Output Disable Control Turns Off Both MOSFETs to
Float Output per Intel® VRM 10 Specification

FUNCTIONAL BLOCK DIAGRAM

VCC

BST
1

4

IN

APPLICATIONS
Multiphase Desktop CPU Supplies
Single-Supply Synchronous Buck Converters

2

8 DRVH
7 SW

OVERLAP
PROTECTION
CIRCUIT

GENERAL DESCRIPTION

The ADP3418 is a dual high voltage MOSFET driver optimized
for driving two N-channel MOSFETs, which are the two switches
in a nonisolated synchronous buck power converter. Each of the
drivers is capable of driving a 3000 pF load with a 20 ns propagation delay and a 30 ns transition time. One of the drivers can
be bootstrapped and is designed to handle the high voltage slew
rate associated with floating high-side gate drivers. The ADP3418
includes overlapping drive protection to prevent shoot-through
current in the external MOSFETs. The OD pin shuts off both
the high-side and the low-side MOSFETs to prevent rapid output
capacitor discharge during system shutdown.

OD

3

5 DRVL

ADP3418
6
PGND

The ADP3418 is specified over the commercial temperature
range of 0°C to 85°C and is available in a thermally enhanced
8-lead SOIC package.

12V

VCC

CVCC

D1

4

ADP3418
BST
1
CBST
IN
DRVH
8

Q1

SW
7
TO INDUCTOR
DELAY
+1V
DRVL
5

Q2

1V
OD

PGND
6

3

Figure 1. General Application Circuit

REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
© 2003 Analog Devices, Inc. All rights reserved.

ADP3418–SPECIFICATIONS1 (VCC = 12 V, BST = 4 V to 26 V, T = 0ⴗC to 85ⴗC, unless otherwise noted.)
A

Parameter

Symbol

Conditions

SUPPLY
Supply Voltage Range
Supply Current

VCC
ISYS

BST = 12 V, IN = 0 V

OD INPUT
Input Voltage High
Input Voltage Low
Input Current
Propagation Delay Time2

LOW-SIDE DRIVER
Output Resistance, Sourcing Current
Output Resistance, Sinking Current
Transition Times2
Propagation Delay2, 3

Max

Unit

3

13.2
6

V
mA

15
20

0.8
+1
30
40

V
V
µA
ns
ns

0.8
+1

V
V
µA

1.8
1.0
35

3.0
2.5
45

Ω
Ω
ns

2.8
–1
tpdlOD
tpdhOD

See Figure 2
See Figure 2
3.5
–1

trDRVH
tfDRVH

Propagation Delay2, 3

Typ

4.15

PWM INPUT
Input Voltage High
Input Voltage Low
Input Current
HIGH-SIDE DRIVER
Output Resistance, Sourcing Current
Output Resistance, Sinking Current
Transition Times2

Min

tpdhDRVH
tpdlDRVH

trDRVL
tfDRVL
tpdhDRVL
tpdlDRVL

VBST – VSW = 12 V
VBST – VSW = 12 V
See Figure 3, VBST – VSW = 12 V,
CLOAD = 3 nF
See Figure 3, VBST – VSW = 12 V,
CLOAD = 3 nF
See Figure 3, VBST – VSW = 12 V
VBST – VSW = 12 V

20

30

ns

40
20

65
35

ns
ns

See Figure 3, CLOAD = 3 nF
See Figure 3, CLOAD = 3 nF
See Figure 3
See Figure 3

1.8
1.0
25
21
30
10

3.0
2.5
35
30
60
20

Ω
Ω
ns
ns
ns
ns

NOTES
1
All limits at temperature extremes are guaranteed via correlation using standard Statistical Quality Control (SQC).
2
AC specifications are guaranteed by characterization but not production tested.
3
For propagation delays, t pdh refers to the specified signal going high, and t pdl refers to it going low.
Specifications subject to change without notice.

–2–

REV. 0

ADP3418
Junction-to-Air Thermal Resistance (θJA)
2-Layer Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123°C/W
4-Layer Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90°C/W
Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . . 300°C
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . 215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C

ABSOLUTE MAXIMUM RATINGS*

VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +15 V
BST . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to VCC + 15 V
BST to SW . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +15 V
SW
DC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –5 V to +15 V
<200 ns . . . . . . . . . . . . . . . . . . . . . . . . . . . . –10 V to +15 V
DRVH . . . . . . . . . . . . . . . . . . . . . . SW – 0.3 V to BST + 0.3 V
DRVL (<200 ns) . . . . . . . . . . . . . . . . . . . –2 V to VCC + 0.3 V
All Other Inputs and Outputs . . . . . . . –0.3 V to VCC + 0.3 V
Operating Ambient Temperature Range . . . . . . . . 0°C to 85°C
Operating Junction Temperature Range . . . . . . . 0°C to 150°C
Storage Temperature Range . . . . . . . . . . . . . –65°C to +150°C

*Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability. Absolute maximum
ratings apply individually only, not in combination. Unless otherwise specified, all
voltages are referenced to PGND.

ORDERING GUIDE

Model

Temperature Range

Package Option

ADP3418JR

0°C to 85°C

RN-8 (SOIC-8)

PIN CONFIGURATION
RN-8
BST 1
IN 2
OD 3

ADP3418
TOP VIEW
(Not to Scale)

VCC 4

8

DRVH

7

SW

6

PGND

5

DRVL

PIN FUNCTION DESCRIPTIONS

Pin No. Mnemonic Description
1

BST

Upper MOSFET Floating Bootstrap Supply. A capacitor connected between the BST and SW pins holds
this bootstrapped voltage for the high-side MOSFET as it is switched. The capacitor should be chosen between
100 nF and 1 µF.

2

IN

Logic Level Input. This pin has primary control of the drive outputs.

3

OD

Output Disable. When low, this pin disables normal operation, forcing DRVH and DRVL low.

4

VCC

Input Supply. This pin should be bypassed to PGND with ~1 µF ceramic capacitor.

5

DRVL

Synchronous Rectifier Drive. Output drive for the lower (synchronous rectifier) MOSFET.

6

PGND

Power Ground. Should be closely connected to the source of the lower MOSFET.

7

SW

This pin is connected to the buck-switching node, close to the upper MOSFET’s source. It is the floating
return for the upper MOSFET drive signal. It is also used to monitor the switched voltage to prevent turn-on of
the lower MOSFET until the voltage is below ~1 V. Thus, according to operating conditions, the high-low
transition delay is determined at this pin.

8

DRVH

Buck Drive. Output drive for the upper (buck) MOSFET.

CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
ADP3418 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended
to avoid performance degradation or loss of functionality.

REV. 0

–3–

ADP3418
TIMING CHARACTERISTICS
OD

tpdlOD

DRVH
OR
DRVL

tpdhOD

90%
10%

Figure 2. Output Disable Timing Diagram

IN

tpdlDRVL tfDRVL
tpdlDRVH

trDRVL

DRVL

tfDRVH
tpdhDRVH trDRVH

VTH

VTH

DRVH-SW

tpdhDRVL
1V

SW

Figure 3. Nonoverlap Timing Diagram (Timing is referenced to the 90% and 10% points, unless otherwise noted.)

–4–

REV. 0

Typical Performance Characteristics–ADP3418
26
VCC = 12V
CLOAD = 3nF

IN
1

24

FALL TIME – ns

DRVL

DRVH
2

22

DRVH

20

DRVL

18
3

16
0

TPC 1. DRVH Rise and DRVL Fall Times

25

50
75
100
JUNCTION TEMPERATURE – ⴗC

125

TPC 4. DRVH and DRVL Fall Times vs. Temperature

60
IN

TA = 25ⴗC
VCC = 12V
DRVH

50

1

RISE TIME – ns

DRVH

2

DRVL

40
DRVL
30

20

3

10
1

TPC 2. DRVH Fall and DRVL Rise Times

2

3
4
LOAD CAPACITANCE – nF

5

TPC 5. DRVH and DRVL Rise Times vs. Load Capacitance

40

35
VCC = 12V
CLOAD = 3nF

TA = 25ⴗC
VCC = 12V

DRVH
30

FALL TIME – ns

RISE TIME – ns

35

30
DRVL

DRVL
25

DRVH

20

25
15

10

20
0

25

50
75
100
JUNCTION TEMPERATURE – ⴗC

125

1

TPC 3. DRVH and DRVL Rise Times vs. Temperature

REV. 0

2

3
4
LOAD CAPACITANCE – nF

5

TPC 6. DRVH and DRVL Fall Times vs. Load Capacitance

–5–

ADP3418
5

60

DRVL OUTPUT VOLTAGE – V

SUPPLY CURRENT – mA

TA = 25ⴗC
VCC = 12V
CLOAD = 3nF

40

20

4

3

2

2

0

0
0

200

400
600
800
IN FREQUENCY – kHz

1000

0

1200

TPC 7. Supply Current vs. Frequency

1

2
3
VCC VOLTAGE – V

4

5

TPC 9. DRVL Output Voltage vs. Supply Voltage

16

SUPPLY CURENT – mA

VCC = 12V
CLOAD = 3nF
fIN = 250kHz
15

14

13

12
0

25

50
75
100
JUNCTION TEMPERATURE – ⴗC

125

TPC 8. Supply Current vs. Temperature

–6–

REV. 0

ADP3418
to fall from VIN to 1 V. Once the voltage on the SW pin has
fallen to 1 V, Q2 will begin turn-on. By waiting for the voltage on
the SW pin to reach 1 V, the overlap protection circuit ensures
that Q1 is off before Q2 turns on, regardless of variations in
temperature, supply voltage, gate charge, and drive current.

THEORY OF OPERATION

The ADP3418 is a dual MOSFET driver optimized for driving
two N-channel MOSFETs in a synchronous buck converter
topology. A single PWM input signal is all that is required to
properly drive the high-side and the low-side MOSFETs. Each
driver is capable of driving a 3 nF load at speeds up to 500 kHz.

To prevent the overlap of the gate drives during Q2’s turn-off
and Q1’s turn-on, the overlap circuit provides an internal delay
that is set to 50 ns. When the PWM input signal goes high, Q2
will begin to turn off (after a propagation delay), but before Q1
can turn on, the overlap protection circuit waits for the voltage
at DRVL to drop to around 10% of VCC. Once the voltage at
DRVL has reached the 10% point, the overlap protection circuit
will wait for a 20 ns typical propagation delay. Once the delay
period has expired, Q1 will begin turn-on.

A more detailed description of the ADP3418 and its features
follows. Refer to the Functional Block Diagram.
Low-Side Driver

The low-side driver is designed to drive a ground-referenced
low RDS(ON) N-channel MOSFET. The bias to the low-side
driver is internally connected to the VCC supply and PGND.
When the driver is enabled, the driver’s output is 180° out of
phase with the PWM input. When the ADP3418 is disabled, the
low-side gate is held low.

APPLICATION INFORMATION
Supply Capacitor Selection

High-Side Driver

For the supply input (VCC) of the ADP3418, a local bypass
capacitor is recommended to reduce the noise and to supply some
of the peak currents drawn. Use a 4.7 µF, low ESR capacitor.
Multilayer ceramic chip (MLCC) capacitors provide the best
combination of low ESR and small size. Keep the ceramic
capacitor as close as possible to the ADP3418.

The high-side driver is designed to drive a floating low RDS(ON)
N-channel MOSFET. The bias voltage for the high-side driver
is developed by an external bootstrap supply circuit, which is
connected between the BST and SW pins.
The bootstrap circuit comprises a diode, D1, and bootstrap
capacitor, CBST. When the ADP3418 is starting up, the SW pin
is at ground, so the bootstrap capacitor will charge up to VCC
through D1. When the PWM input goes high, the high-side
driver will begin to turn on the high-side MOSFET, Q1, by
pulling charge out of CBST. As Q1 turns on, the SW pin will rise
up to VIN, forcing the BST pin to VIN + VC(BST), which is enough
gate-to-source voltage to hold Q1 on. To complete the cycle,
Q1 is switched off by pulling the gate down to the voltage at the
SW pin. When the low-side MOSFET, Q2, turns on, the SW
pin is pulled to ground. This allows the bootstrap capacitor to
charge up to VCC again.

Bootstrap Circuit

The bootstrap circuit uses a charge storage capacitor (CBST) and
a diode, as shown in Figure 1. Selection of these components
can be done after the high-side MOSFET has been chosen.
The bootstrap capacitor must have a voltage rating that is able
to handle twice the maximum supply voltage. A minimum 50 V
rating is recommended. The capacitance is determined using
the following equation
Q
CBST = GATE
(1)
∆VBST

The high-side driver’s output is in phase with the PWM input.
When the driver is disabled, the high-side gate is held low.

where QGATE is the total gate charge of the high-side MOSFET,
and ∆VBST is the voltage droop allowed on the high-side MOSFET
drive. For example, an IPD30N06 has a total gate charge of
about 20 nC. For an allowed droop of 200 mV, the required
bootstrap capacitance is 100 nF. A good quality ceramic capacitor should be used.

Overlap Protection Circuit

The overlap protection circuit prevents both of the main power
switches, Q1 and Q2, from being on at the same time. This is
done to prevent shoot-through currents from flowing through
both power switches and the associated losses that can occur
during their on-off transitions. The overlap protection circuit
accomplishes this by adaptively controlling the delay from Q1’s
turn-off to Q2’s turn-on and by internally setting the delay from
Q2’s turn-off to Q1’s turn-on.

A small-signal diode can be used for the bootstrap diode due to
the ample gate drive voltage supplied by VCC. The bootstrap diode
must have a minimum 15 V rating to withstand the maximum
supply voltage. The average forward current can be estimated by
I F ( AVG ) = QGATE × f MAX
(2)

To prevent the overlap of the gate drives during Q1’s turn-off
and Q2’s turn-on, the overlap circuit monitors the voltage at the
SW pin. When the PWM input signal goes low, Q1 will begin to
turn-off (after a propagation delay), but before Q2 can turn on,
the overlap protection circuit waits for the voltage at the SW pin

REV. 0

where fMAX is the maximum switching frequency of the controller. The peak surge current rating should be checked in-circuit,
since this is dependent on the source impedance of the 12 V
supply and the ESR of CBST.

–7–

ADP3418
L1
1.6␮H
VIN
12V

470␮F/16V ⴛ 6
NICHICON PW SERIES
+

+

C1

C9
4.7␮F

D2
1N4148WS

VIN RTN
C6

U2
C8
ADP3418 100nF

D1
1N4148WS

1

BST

DRVH

8

2

IN

SW

7

3

OD

PGND

6

4

VCC

DRVL

5

Q1
IPD12N03L

820␮F/2.5V ⴛ 8
L2
FUJITSU RE SERIES
600nH/1.6m⍀ 14m⍀ ESR (EACH)
C10
4.7nF

C7
4.7␮F

D3
1N4148WS

BST

2

DRVH

8

SW

7

IN

3
4

OD

PGND

6

VCC

DRVL

5

Q4
IPD12N03L

L3
600nH/1.6m⍀

R2
2.2⍀

D4
1N4148WS

U4

Q6
IPD06N03L

C17
4.7␮F

C16

ADP3418 100nF
1

BST

2

IN

3
4

DRVH

8

SW

7

OD

PGND

6

VCC

DRVL

5

Q7
IPD12N03L

L4
600nH/1.6m⍀
C18
4.7nF

RTH
100k⍀, 5%

R3
2.2⍀

C15
4.7␮F
Q8
IPD06N03L

Q9
IPD06N03L

+ C20

C19
1␮F

FROM CPU

33␮F

CB
1.5nF
CFB
33pF
CA
RA
390pF 16.9k⍀

ENABLE

CDLY
39nF

C28

C14
4.7nF

Q5
IPD06N03L

RB
1.33k⍀

0.8375V – 1.6V
65A AVG, 74A PK

10␮F ⴛ 20
MLCC
IN
SOCKET

C11
4.7␮F

POWER
GOOD

C21

C13
4.7␮F

C12
U3
ADP3418 100nF
1

+

VCC(CORE) RTN

R1
2.2⍀
Q3
IPD06N03L

Q2
IPD06N03L

R4
10⍀

+

VCC(CORE)

RDLY
390k⍀
RT
249k⍀

RR
412k⍀

U1
ADP3168

1

VID4

VCC 28

2

VID3

PWM1 27

3

VID2

PWM2 26

4

VID1

PWM3 25

5

VID0

PWM4 24

6

VID5

SW1 23

7

FBRTN

SW2 22

8

FB

SW3 21

9

COMP

SW4 20

10

PWRGD

11

EN

12

DELAY

CSSUM 17

13

RT

CSREF 16

14

RAMPADJ

RSW1
RSW2

RPH1
124k⍀

RSW3

GND 19
CSCOMP 18

CCS2 RCS1
1.5nF 35.7k⍀

RPH3
124k⍀
RCS2

73.2k⍀

RPH2
124k⍀

CCS1
2.2nF

ILIMIT 15
RLIM
200k⍀

Figure 4. VRD 10 Compliant Intel CPU Supply Circuit

–8–

REV. 0

ADP3418
PC BOARD LAYOUT CONSIDERATIONS

CBST

D1

Use the following general guidelines when designing printed
circuit boards.
1. Trace out the high current paths and use short, wide (>20 mil)
traces to make these connections.
2. Connect the PGND pin of the ADP3418 as close as possible
to the source of the lower MOSFET.
3. The VCC bypass capacitor should be located as close as
possible to the VCC and PGND pins.
4. Use vias to other layers when possible to maximize thermal
conduction away from the IC.
The circuit in Figure 4 shows how three drivers can be combined
with the ADP3168 to form a total power conversion solution for
generating VCC(CORE) for an Intel CPU that is VRD 10 compliant.
Figure 5 gives an example of the typical land patterns based on the
guidelines given previously. For more detailed layout guidelines
for a complete CPU voltage regulator subsystem, refer to the
ADP3168 data sheet.

REV. 0

CVCC

Figure 5. External Component Placement
Example for the ADP3418 Driver

–9–

ADP3418
OUTLINE DIMENSIONS
8-Lead Standard Small Outline Package [SOIC]
(RN-8)
Dimensions shown in millimeters and (inches)
5.00 (0.1968)
4.80 (0.1890)

4.00 (0.1574)
3.80 (0.1497)

8

5

1

4

1.27 (0.0500)
BSC
0.25 (0.0098)
0.10 (0.0040)
COPLANARITY
SEATING
0.10
PLANE

6.20 (0.2440)
5.80 (0.2284)

1.75 (0.0688)
1.35 (0.0532)

0.51 (0.0201)
0.33 (0.0130)

0.50 (0.0196)
ⴛ45ⴗ
0.25 (0.0099)

8ⴗ
0.25 (0.0098) 0ⴗ 1.27 (0.0500)
0.41 (0.0160)
0.19 (0.0075)

COMPLIANT TO JEDEC STANDARDS MS-012AA
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN

–10–

REV. 0

–11–

–12–
C03229–0–3/03(0)