September 2001

FDC6301N
Dual N-Channel , Digital FET
General Description

Features

These dual N-Channel logic level enhancement mode field
effect transistors are produced using Fairchild 's proprietary,
high cell density, DMOS technology. This very high density
process is especially tailored to minimize on-state resistance.
This device has been designed especially for low voltage
applications as a replacement for digital transistors. Since bias
resistors are not required, these N-Channel FET's can replace
several digital transistors, with a variety of bias resistors.

SOT-23

TM
SuperSOT -8

TM
SuperSOT -6

25 V, 0.22 A continuous, 0.5 A Peak.
RDS(ON) = 5 Ω @ VGS= 2.7 V
RDS(ON) = 4 Ω @ VGS= 4.5 V.
Very low level gate drive requirements allowing direct
operation in 3V circuits. VGS(th) < 1.5V.
Gate-Source Zener for ESD ruggedness.
>6kV Human Body Model.

SO-8

SOIC-16

SOT-223

Mark: .301

INVERTER APPLICATION

4

3

5

2

6

1

Vcc

D

OUT

Absolute Maximum Ratings

G

S
GND

TA = 25oC unless other wise noted

Symbol

Parameter

VDSS, VCC

Drain-Source Voltage, Power Supply Voltage

VGSS, VIN

Gate-Source Voltage, VIN

ID, IOUT

Drain/Output Current

PD

IN

FDC6301N
25
- 0.5 to +8
- Continuous

0.22

- Pulsed

0.5

Maximum Power Dissipation

(Note 1a)
(Note 1b)

TJ,TSTG

Operating and Storage Temperature Range

ESD

Electrostatic Discharge Rating MIL-STD-883D
Human Body Model (100pf / 1500 Ohm)

0.9

Units
V
V
A

W

0.7
-55 to 150

°C

6.0

kV

THERMAL CHARACTERISTICS
RθJA

Thermal Resistance, Junction-to-Ambient

(Note 1a)

140

°C/W

RθJC

Thermal Resistance, Junction-to-Case

(Note 1)

60

°C/W

© 2001 Fairchild Semiconductor Corporation

FDC6301N Rev.D

Electrical Characteristics (TA = 25 OC unless otherwise noted )
Symbol

Parameter

Conditions

Min

Typ

Max

Units

OFF CHARACTERISTICS
BVDSS

Drain-Source Breakdown Voltage

VGS = 0 V, ID = 250 µA

∆BVDSS/∆TJ

Breakdown Voltage Temp. Coefficient

ID = 250 µA, Referenced to 25 o C

25

IDSS

Zero Gate Voltage Drain Current

VDS = 20 V, VGS = 0 V

IGSS

Gate - Body Leakage Current

VGS = 8 V, VDS= 0 V

V
mV /oC

25

TJ = 55°C

1

µA

10

µA

100

nA

ON CHARACTERISTICS (Note 2)

∆VGS(th)/∆TJ

Gate Threshold Voltage Temp.Coefficient

ID = 250 µA, Referenced to 25 o C

VGS(th)

Gate Threshold Voltage

VDS = VGS, ID = 250 µA

RDS(ON)

Static Drain-Source On-Resistance

VGS = 2.7 V, ID = 0.2 A

mV /oC

-2.1
0.65

TJ =125°C
VGS = 4.5 V, ID = 0.4 A

0.85

1.5

V

3.8

5

Ω

6.3

9

3.1

4

ID(ON)

On-State Drain Current

VGS = 2.7 V, VDS = 5 V

gFS

Forward Transconductance

VDS = 5 V, ID= 0.4 A

0.25

S

VDS = 10 V, VGS = 0 V,
f = 1.0 MHz

9.5

pF

0.2

A

DYNAMIC CHARACTERISTICS
Ciss

Input Capacitance

Coss

Output Capacitance

Crss

Reverse Transfer Capacitance

6

pF

1.3

pF

SWITCHING CHARACTERISTICS (Note 2)
tD(on)

Turn - On Delay Time

tr

Turn - On Rise Time

tD(off)

Turn - Off Delay Time

tf

Turn - Off Fall Time

Qg

Total Gate Charge

Qgs

Gate-Source Charge

Qgd

Gate-Drain Charge

VDD = 6 V, ID = 0.5 A,
VGS = 4.5 V, RGEN = 50 Ω

VDS = 5 V, ID = 0.2 A,
VGS = 4.5 V

5

10

ns

4.5

10

ns

4

8

ns

3.2

7

ns

0.49

0.7

nC

0.22

nC

0.07

nC

Inverter Electrical Characteristics (TA = 25°C unless otherwise noted)
IO (off)

Zero Input Voltage Output Current

VCC = 20 V, VI = 0 V

1

µA

VI (off)

Input Voltage

VCC = 5 V, IO = 10 µA

0.5

V

VO = 0.3 V, IO = 0.005 A

VI (on)
RO (on)

Output to Ground Resistance

VI = 2.7 V, IO = 0.2 A

1

V
3.8

5

Ω

Notes:
1. RθJA is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. RθJC is guaranteed by
design while RθCA is determined by the user's board design. RθJA shown below for single device operation on FR-4 in still air.

a. 140OC/W on a 0.125 in2 pad of
2oz copper.

b. 180OC/W on a 0.005 in2 of pad
of 2oz copper.

2. Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0%.

FDC6301N Rev.D

Typical Electrical Characteristics
3.5

R DS(on ) , NORMALIZED

3.0
0.4

2.7
2.5

0.3

0.2

2.0

0.1

1.5

I

DRAIN-SOURCE ON-RESISTANCE

1.4

V GS = 4.5V

D

, DRAIN-SOURCE CURRENT (A)

0.5

VGS = 2.0V
1.2

2.5

0

1
V

DS

2
3
4
, DRAIN-SOURCE VOLTAGE (V)

3.0
3.5
4.0

0.8

0.6

0

2.7

1

5

4.5

0

0.4

0.5

15
R DS(on) , ON-RESISTANCE (OHM)

I D = 0.2A

1.6

V GS = 2.7 V

1.4

1.2

1

0.8

-25

0
25
50
75
100
TJ , JUNCTION TEMPERATURE (°C)

125

12

125°C
9

6

3

150

4

4.5

5

I S, REVERSE DRAIN CURRENT (A)

V GS = 0V

0.15

0.1

0.05

Figure 5. Transfer Characteristics.

3.5

0.5

T = -55°C
J
25°C

1
1.5
2
V GS , GATE TO SOURCE VOLTAGE (V)

3

Gate-To- Source Voltage.

125°C

0
0.5

2.5

Figure 4. On Resistance Variation with

with Temperature.

V DS = 5.0V

2

V GS , GATE TO SOURCE VOLTAGE (V)

Figure 3. On-Resistance Variation

0.2

I D = 0.2A

25°C

0

0.6
-50

I D , DRAIN CURRENT (A)

0.3

Figure 2. On-Resistance Variation with
Drain Current and Gate Voltage.

1.8

R DS(ON), NORMALIZED

0.2

ID , DRAIN CURRENT (A)

Figure 1. On-Region Characteristics.

DRAIN-SOURCE ON-RESISTANCE

0.1

2.5

0.2
0.1

TJ = 125°C
25°C

0.01

-55°C

0.001

0.0001
0.2

0.4
0.6
0.8
1
V SD , BODY DIODE FORWARD VOLTAGE (V)

1.2

Figure 6. Body Diode Forward Voltage
Variation with Source Current and Temperature.

FDC6301N Rev.D

5

30

VDS = 5V

I D = 0.2A

20

10V

4

15V
CAPACITANCE (pF)

V GS , GATE-SOURCE VOLTAGE (V)

Typical Electrical Characteristics (continued)

3

2

C iss

10

C oss

5

3

f = 1 MHz

2

1

0

V GS = 0V
1
0.1

0

0.1

0.2

0.3

0.4

0.5

C rss
0.5

0.6

1

2

5

10

25

V
, DRAIN TO SOURCE VOLTAGE (V)
DS

Qg , GATE CHARGE (nC)

Figure 8. Capacitance Characteristics.

Figure 7. Gate Charge Characteristics.

1

5

1m
10 s
ms

IT
LIM
N)
(O
S
RD

10

0m

s

1s

0.1

DC
0.05

0.02

V GS = 2.7V
SINGLE PULSE
RθJA =See note 1b
TA = 25°C

0.01
0.5

1
DS

3

2

1

2
V

SINGLE PULSE
RθJA =See note 1b
TA = 25°C

4
POWER (W)

0.2

5

10

15

25

0
0.01

35

0.1

1

10

100

300

SINGLE PULSE TIME (SEC)

, DRAI N-SOURCE VOLTAGE (V)

Figure 10. Single Pulse Maximum Power
Dissipation.

Figure 9. Maximum Safe Operating Area.

1
r(t), NORMALIZED EFFECTIVE
TRANSIENT THERMAL RESISTANCE

ID , DRAIN CURRENT (A)

0.5

0.5

D = 0.5

0.2

0.2

0.1
0.05

0.02
0.01
0.0001

RθJA (t) = r(t) * R θJA
R θJA = See Note 1b

0.1
P(pk)
0.05

t1

0.02
0.01
Single Pulse

0.001

t2

TJ - TA = P * R JA(t)
θ
Duty Cycle, D = t 1/ t 2
0.01

0.1

1

10

100

300

t 1, TIME (sec)

Figure 11. Transient Thermal Response Curve.
Note: Thermal characterization performed using the conditions described in note 1b.Transient thermal
response will change depending on the circuit board design.

FDC6301N Rev.D

TRADEMARKS
The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is
not intended to be an exhaustive list of all such trademarks.

ACEx™
Bottomless™
CoolFET™
CROSSVOLT™
DenseTrench™
DOME™
EcoSPARK™
E2CMOSTM
EnSignaTM
FACT™
FACT Quiet Series™

FAST â
FASTr™
FRFET™
GlobalOptoisolator™
GTO™
HiSeC™
I2C™
ISOPLANAR™
LittleFET™
MicroFET™
MicroPak™

MICROWIRE™
OPTOLOGIC â
OPTOPLANAR™
PACMAN™
POP™
Power247™
PowerTrench â
QFET™
QS™
QT Optoelectronics™
Quiet Series™

SILENT SWITCHER â UHC™
SMART START™
UltraFET â
SPM™
VCX™
STAR*POWER™
Stealth™
SuperSOT™-3
SuperSOT™-6
SuperSOT™-8
SyncFET™
TinyLogic™
TruTranslation™

STAR*POWER is used under license

DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER
NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD
DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT
OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT
RIGHTS, NOR THE RIGHTS OF OTHERS.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION.
As used herein:
2. A critical component is any component of a life
1. Life support devices or systems are devices or
support device or system whose failure to perform can
systems which, (a) are intended for surgical implant into
be reasonably expected to cause the failure of the life
the body, or (b) support or sustain life, or (c) whose
support device or system, or to affect its safety or
failure to perform when properly used in accordance
with instructions for use provided in the labeling, can be
effectiveness.
reasonably expected to result in significant injury to the
user.
PRODUCT STATUS DEFINITIONS
Definition of Terms
Datasheet Identification

Product Status

Definition

Advance Information

Formative or
In Design

This datasheet contains the design specifications for
product development. Specifications may change in
any manner without notice.

Preliminary

First Production

This datasheet contains preliminary data, and
supplementary data will be published at a later date.
Fairchild Semiconductor reserves the right to make
changes at any time without notice in order to improve
design.

No Identification Needed

Full Production

This datasheet contains final specifications. Fairchild
Semiconductor reserves the right to make changes at
any time without notice in order to improve design.

Obsolete

Not In Production

This datasheet contains specifications on a product
that has been discontinued by Fairchild semiconductor.
The datasheet is printed for reference information only.

Rev. H5

www.s-manuals.com