CA3130, CA3130A

®

Data Sheet

FN817.6

15MHz, BiMOS Operational Amplifier with
MOSFET Input/CMOS Output
CA3130A and CA3130 are op amps that combine the
advantage of both CMOS and bipolar transistors.
Gate-protected P-Channel MOSFET (PMOS) transistors are
used in the input circuit to provide very-high-input
impedance, very-low-input current, and exceptional speed
performance. The use of PMOS transistors in the input stage
results in common-mode input-voltage capability down to
0.5V below the negative-supply terminal, an important
attribute in single-supply applications.
A CMOS transistor-pair, capable of swinging the output
voltage to within 10mV of either supply-voltage terminal (at
very high values of load impedance), is employed as the
output circuit.
The CA3130 Series circuits operate at supply voltages
ranging from 5V to 16V, (±2.5V to ±8V). They can be phase
compensated with a single external capacitor, and have
terminals for adjustment of offset voltage for applications
requiring offset-null capability. Terminal provisions are also
made to permit strobing of the output stage.

Features
• MOSFET Input Stage Provides:
- Very High ZI = 1.5 TΩ (1.5 x 1012Ω) (Typ)
- Very Low II . . . . . . . . . . . . . 5pA (Typ) at 15V Operation
. . . . . . . . . . . . . . . . . . . . . .= 2pA (Typ) at 5V Operation
• Ideal for Single-Supply Applications
• Common-Mode Input-Voltage Range Includes
Negative Supply Rail; Input Terminals can be Swung 0.5V
Below Negative Supply Rail
• CMOS Output Stage Permits Signal Swing to Either (or
both) Supply Rails
• Pb-Free Plus Anneal Available (RoHS Compliant)

Applications
• Ground-Referenced Single Supply Amplifiers
• Fast Sample-Hold Amplifiers
• Long-Duration Timers/Monostables
• High-Input-Impedance Comparators
(Ideal Interface with Digital CMOS)
• High-Input-Impedance Wideband Amplifiers

• The CA3130A offers superior input characteristics over
those of the CA3130.

Ordering Information
PART NO.
(BRAND)
CA3130AE
CA3130AM

TEMP.
RANGE (oC)
PACKAGE
-55 to 125 8 Ld PDIP
-55 to 125 8 Ld SOIC

PKG.
DWG. #
E8.3
M8.15

(3130A)
CA3130AM96

-55 to 125

(3130A)
CA3130AMZ

-55 to 125

(3130AZ) (Note)
CA3130AMZ96

-55 to 125

(3130AZ) (Note)
CA3130E
CA3130EZ
(Note)
CA3130M

-55 to 125
-55 to 125
-55 to 125

8 Ld SOIC
Tape and Reel
8 Ld SOIC
(Pb-free)
8 Ld SOIC
Tape and Reel (Pb-free)
8 Ld PDIP
8 Ld PDIP*
(Pb-free)
8 Ld SOIC

M8.15
M8.15

-55 to 125

(3130)
CA3130MZ

-55 to 125

(3130MZ) (Note)
CA3130MZ96

(3130MZ)

-55 to 125

E8.3
E8.3
M8.15

8 Ld SOIC
M8.15
Tape and Reel
8 Ld SOIC
M8.15
(Pb-free)
8 Ld SOIC
M8.15
Tape and Reel (Pb-free)

*Pb-free PDIPs can be used for through hole wave solder processing only. They are not
intended for use in Reflow solder processing applications.
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets;
molding compounds/die attach materials and 100% matte tin plate termination finish,
which are RoHS compliant and compatible with both SnPb and Pb-free soldering
operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow
temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

1

• Voltage Regulators (Permits Control of Output Voltage
Down to 0V)
• Peak Detectors
• Single-Supply Full-Wave Precision Rectifiers
• Photo-Diode Sensor Amplifiers

Pinout
CA3130, CA3130A
(PDIP, SOIC)
TOP VIEW

M8.15

(3130)
CA3130M96

• Voltage Followers (e.g. Follower for Single-Supply D/A
Converter)

OFFSET
NULL
INV.
INPUT
NON-INV.
INPUT

1

V-

4

8

STROBE

2

-

7

V+

3

+

6

OUTPUT

5

OFFSET
NULL

CA3130, CA3130A
Absolute Maximum Ratings

Thermal Information

DC Supply Voltage (Between V+ And V- Terminals) . . . . . . . . . .16V
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8V
DC Input Voltage . . . . . . . . . . . . . . . . . . . . . . (V+ +8V) to (V- -0.5V)
Input-Terminal Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1mA
Output Short-Circuit Duration (Note 1) . . . . . . . . . . . . . . . Indefinite

Thermal Resistance (Typical, Note 2)
θJA (oC/W) θJC (oC/W)
PDIP Package*. . . . . . . . . . . . . . . . . . .
115
N/A
SOIC Package . . . . . . . . . . . . . . . . . . .
160
N/A
Maximum Junction Temperature (Plastic Package) . . . . . . . .150oC
Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300oC
(SOIC - Lead Tips Only)
*Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing
applications.

Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . -50oC to 125oC

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTES:
1. Short circuit may be applied to ground or to either supply.
2. θJA is measured with the component mounted on an evaluation PC board in free air.
TA = 25oC, V+ = 15V, V- = 0V, Unless Otherwise Specified

Electrical Specifications
PARAMETER

SYMBOL

TEST
CONDITIONS
VS = ±7.5V

CA3130

CA3130A

MIN

TYP

MAX

MIN

TYP

MAX

UNITS

-

8

15

-

2

5

mV

-

10

-

-

10

-

µV/oC

Input Offset Voltage

|VIO|

Input Offset Voltage
Temperature Drift

∆VIO/∆T

Input Offset Current

|IIO|

VS = ±7.5V

-

0.5

30

-

0.5

20

pA

II

VS = ±7.5V

-

5

50

-

5

30

pA

50

320

-

50

320

-

kV/V

94

110

-

94

110

-

dB

CMRR

70

90

-

80

90

-

dB

VICR

0

-0.5 to 12

10

0

-0.5 to 12

10

V

-

32

320

-

32

150

µV/V

Input Current
Large-Signal Voltage Gain

AOL

Common-Mode
Rejection Ratio
Common-Mode Input
Voltage Range

∆VIO/∆VS

Power-Supply
Rejection Ratio
Maximum Output Voltage

Maximum Output Current

VO = 10VP-P
RL = 2kΩ

VS = ±7.5V

VOM+

RL = 2kΩ

12

13.3

-

12

13.3

-

V

VOM-

RL = 2kΩ

-

0.002

0.01

-

0.002

0.01

V

VOM+

RL = ∞

14.99

15

-

14.99

15

-

V

VOM-

RL = ∞

-

0

0.01

-

0

0.01

V

IOM+ (Source) at VO = 0V

12

22

45

12

22

45

mA

IOM- (Sink) at VO = 15V

12

20

45

12

20

45

mA

Supply Current

2

I+

VO = 7.5V,
RL = ∞

-

10

15

-

10

15

mA

I+

VO = 0V,
RL = ∞

-

2

3

-

2

3

mA

CA3130, CA3130A
Typical Values Intended Only for Design Guidance, VSUPPLY = ±7.5V, TA = 25oC
Unless Otherwise Specified

Electrical Specifications

PARAMETER

SYMBOL

Input Offset Voltage Adjustment Range

TEST CONDITIONS
10kΩ Across Terminals 4 and 5 or
4 and 1

CA3130,
CA3130A

UNITS

±22

mV

1.5

TΩ

Input Resistance

RI

Input Capacitance

CI

f = 1MHz

4.3

pF

Equivalent Input Noise Voltage

eN

BW = 0.2MHz, RS = 1MΩ
(Note 3)

23

µV

Open Loop Unity Gain Crossover Frequency
(For Unity Gain Stability ≥47pF Required.)

CC = 0

15

MHz

fT

CC = 47pF

4

MHz

Slew Rate:

SR

Open Loop

CC = 0

30

V/µs

Closed Loop

CC = 56pF

10

V/µs

0.09

µs

10

%

1.2

µs

Transient Response:
Rise Time

tr

Overshoot

OS

Settling Time (To <0.1%, VIN = 4VP-P)

CC = 56pF,
CL = 25pF,
RL = 2kΩ
(Voltage Follower)

tS

NOTE:
3. Although a 1MΩ source is used for this test, the equivalent input noise remains constant for values of RS up to 10MΩ.
Typical Values Intended Only for Design Guidance, V+ = 5V, V- = 0V, TA = 25oC
Unless Otherwise Specified (Note 4)

Electrical Specifications
PARAMETER

SYMBOL

TEST CONDITIONS

CA3130

CA3130A

UNITS

Input Offset Voltage

VIO

8

2

mV

Input Offset Current

IIO

0.1

0.1

pA

II

2

2

pA

CMRR

80

90

dB

100

100

kV/V

100

100

dB

0 to 2.8

0 to 2.8

V

VO = 5V, RL = ∞

300

300

µA

VO = 2.5V, RL = ∞

500

500

µA

200

200

µV/V

Input Current
Common-Mode Rejection Ratio
Large-Signal Voltage Gain

AOL

Common-Mode Input Voltage Range
Supply Current

VO = 4VP-P, RL = 5kΩ

VICR
I+

∆VIO/∆V+

Power Supply Rejection Ratio
NOTE:

4. Operation at 5V is not recommended for temperatures below 25oC.

3

CA3130, CA3130A
Dual-In-Line Plastic Packages (PDIP)
E8.3 (JEDEC MS-001-BA ISSUE D)

N

8 LEAD DUAL-IN-LINE PLASTIC PACKAGE

E1
INDEX
AREA

1 2 3

INCHES

N/2
-B-

-AD

E

BASE
PLANE

-C-

A2

SEATING
PLANE

A
L

D1

e

B1

D1

A1

eC

B
0.010 (0.25) M

C A B S

MILLIMETERS

SYMBOL

MIN

MAX

MIN

MAX

NOTES

A

-

0.210

-

5.33

4

A1

0.015

-

0.39

-

4

A2

0.115

0.195

2.93

4.95

-

B

0.014

0.022

0.356

0.558

-

C
L

B1

0.045

0.070

1.15

1.77

8, 10

eA

C

0.008

0.014

0.204

C

D

0.355

0.400

9.01

eB

NOTES:
1. Controlling Dimensions: INCH. In case of conflict between
English and Metric dimensions, the inch dimensions control.

0.005

-

0.13

-

5

E

0.300

0.325

7.62

8.25

6

E1

0.240

0.280

6.10

7.11

5

e

0.100 BSC

eA

0.300 BSC

3. Symbols are defined in the “MO Series Symbol List” in Section
2.2 of Publication No. 95.

eB

-

L

0.115

5. D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 inch
(0.25mm).
6. E and eA are measured with the leads constrained to be perpendicular to datum -C- .
7. eB and eC are measured at the lead tips with the leads unconstrained. eC must be zero or greater.
8. B1 maximum dimensions do not include dambar protrusions.
Dambar protrusions shall not exceed 0.010 inch (0.25mm).
9. N is the maximum number of terminal positions.
10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3,
E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch
(0.76 - 1.14mm).

16

5

D1

2. Dimensioning and tolerancing per ANSI Y14.5M-1982.

4. Dimensions A, A1 and L are measured with the package seated
in JEDEC seating plane gauge GS-3.

0.355
10.16

N

8

2.54 BSC
7.62 BSC

0.430

-

0.150

2.93

10.92
3.81
8

6
7
4
9
Rev. 0 12/93

CA3130, CA3130A
Small Outline Plastic Packages (SOIC)
M8.15 (JEDEC MS-012-AA ISSUE C)

N
INDEX
AREA

8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE
H

0.25(0.010) M

B M

INCHES

E

SYMBOL

-B1

2

3

L
SEATING PLANE

-A-

A

D

h x 45°

-C-

e

A1

B
0.25(0.010) M

C
0.10(0.004)

C A M

MIN

MAX

MIN

MAX

NOTES

A

0.0532

0.0688

1.35

1.75

-

A1

0.0040

0.0098

0.10

0.25

-

B

0.013

0.020

0.33

0.51

9

C

0.0075

0.0098

0.19

0.25

-

D

0.1890

0.1968

4.80

5.00

3

E

0.1497

0.1574

3.80

4.00

4

e

α

B S

0.050 BSC

2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per
side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact.

17

-

0.2284

0.2440

5.80

6.20

-

h

0.0099

0.0196

0.25

0.50

5

L

0.016

0.050

0.40

α

1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.

1.27 BSC

H

N

NOTES:

MILLIMETERS

8
0°

1.27
8

8°

0°

6
7

8°

Rev. 1 6/05