BSS123 N-Channel Logic Level Enhancement Mode Field Effect Transistor General Description Features These N-Channel enhancement mode field effect transistors are produced using Fairchild’s proprietary, high cell density, DMOS technology. These products have been designed to minimize on-state resistance while provide rugged, reliable, and fast switching performance.These products are particularly suited for low voltage, low current applications such as small servo motor control, power MOSFET gate drivers, and other switching applications. • 0.17 A, 100 V. RDS(ON) = 6Ω @ VGS = 10 V RDS(ON) = 10Ω @ VGS = 4.5 V • High density cell design for extremely low RDS(ON) • Rugged and Reliable • Compact industry standard SOT-23 surface mount package D D S S G SOT-23 G Absolute Maximum Ratings Symbol TA=25oC unless otherwise noted Ratings Units VDSS Drain-Source Voltage Parameter 100 V VGSS Gate-Source Voltage ±20 V ID Drain Current 0.17 A – Continuous (Note 1) – Pulsed 0.68 Maximum Power Dissipation PD (Note 1) Derate Above 25°C TJ, TSTG Operating and Storage Junction Temperature Range Maximum Lead Temperature for Soldering Purposes, 1/16” from Case for 10 Seconds TL 0.36 2.8 W mW/°C −55 to +150 °C 300 Thermal Characteristics Thermal Resistance, Junction-to-Ambient RθJA (Note 1) 350 °C/W Package Marking and Ordering Information Device Marking Device Reel Size Tape width Quantity SA BSS123 7’’ 8mm 3000 units 2003 Fairchild Semiconductor Corporation BSS123 Rev G(W) BSS123 June 2003 Symbol Parameter TA = 25°C unless otherwise noted Test Conditions Min Typ Max Units Off Characteristics ID = 250 µA BVDSS Drain–Source Breakdown Voltage VGS = 0 V, ∆BVDSS ∆TJ IDSS Breakdown Voltage Temperature Coefficient Zero Gate Voltage Drain Current ID = 250 µA,Referenced to 25°C VDS = 100 V, 100 V 97 VGS = 0 V VDS = 100 V,VGS = 0 V TJ = 125°C IGSS Gate–Body Leakage. On Characteristics mV/°C 1 µA 60 µA VDS = 20 V, VGS = 0 V 10 nA VGS = ±20 V, VDS = 0 V ±50 nA (Note 2) VGS(th) ∆VGS(th) ∆TJ RDS(on) Gate Threshold Voltage Gate Threshold Voltage Temperature Coefficient Static Drain–Source On–Resistance ID(on) gFS VDS = VGS, ID = 1 mA 0.8 ID = 1 mA,Referenced to 25°C On–State Drain Current VGS = 10 V, ID = 0.17 A VGS = 4.5 V, ID = 0.17 A VGS = 10 V, ID = 0.17 A, TJ = 125°C VGS = 10 V, VDS = 5 V 0.68 Forward Transconductance VDS = 10V, ID = 0.17 A 0.08 VDS = 25 V, f = 1.0 MHz V GS = 0 V, 1.7 –2.7 2 1.2 1.3 2.2 6 10 12 V mV/°C Ω A 0.8 S 73 pF 7 pF 3.4 pF VGS = 15 mV, f = 1.0 MHz 2.2 Ω VDD = 30 V, VGS = 10 V, 1.7 3.4 9 18 ns 31 ns Dynamic Characteristics Ciss Input Capacitance Coss Output Capacitance Crss Reverse Transfer Capacitance RG Gate Resistance Switching Characteristics (Note 2) td(on) Turn–On Delay Time tr Turn–On Rise Time td(off) Turn–Off Delay Time 17 tf Turn–Off Fall Time 2.4 5 ns Qg Total Gate Charge 1.8 2.5 nC Qgs Gate–Source Charge Qgd Gate–Drain Charge VDS = 30 V, VGS = 10 V ID = 0.28 A, RGEN = 6 Ω ID = 0.22 A, ns 0.2 nC 0.3 nC Drain–Source Diode Characteristics and Maximum Ratings IS Maximum Continuous Drain–Source Diode Forward Current VSD trr Drain–Source Diode Forward Voltage Diode Reverse Recovery Time Qrr Diode Reverse Recovery Charge VGS = 0 V, IS = 0.34 A(Note 2) IF = 0.17 A, diF/dt = 100 A/µs 0.8 0.17 A 1.3 V 11 nS 3 nC NOTE: 1. RθJA is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. RθJC is guaranteed by design while RθCA is determined by the user's board design. a) 350°C/W when mounted on a minimum pad.. Scale 1 : 1 on letter size paper 2. Pulse Test: Pulse Width ≤ 300 µs, Duty Cycle ≤ 2.0% BSS123 Rev G(W) BSS123 Electrical Characteristics BSS123 Typical Characteristics 1 1.6 VGS = 10V RDS(ON), NORMALIZED DRAIN-SOURCE ON-RESISTANCE 3.5V 6.0V ID, DRAIN CURRENT (A) 0.8 4.5V 3.0V 2.5V 0.6 0.4 0.2 2.0V 1 2 3 4 1.4 VGS = 2.5V 1.3 1.2 3.0V 1.1 3.5V 0 5 0.2 Figure 1. On-Region Characteristics. 10V 0.4 0.6 0.8 1 Figure 2. On-Resistance Variation with Drain Current and Gate Voltage. 2.2 3.4 ID = 170mA VGS = 10V 2 RDS(ON), ON-RESISTANCE (OHM) RDS(ON), NORMALIZED DRAIN-SOURCE ON-RESISTANCE 6.0V ID, DRAIN CURRENT (A) VDS, DRAIN TO SOURCE VOLTAGE (V) 1.8 1.6 1.4 1.2 1 0.8 0.6 ID = 0.08A 3 TA = 125oC 2.6 2.2 1.8 1.4 TA = 25oC 1 0.4 -50 -25 0 25 50 75 100 125 0 150 2 o 4 6 8 10 VGS, GATE TO SOURCE VOLTAGE (V) TJ, JUNCTION TEMPERATURE ( C) Figure 3. On-Resistance Variation with Temperature. Figure 4. On-Resistance Variation with Gate-to-Source Voltage. 1 IS, REVERSE DRAIN CURRENT (A) 1 VDS = 10V ID, DRAIN CURRENT (A) 4.5V 1 0.9 0 0 1.5 0.8 0.6 0.4 TA = 125oC 25oC 0.2 -55oC VGS = 0V 0.1 TA = 125oC 25oC 0.01 -55oC 0.001 0.0001 0 1 1.5 2 2.5 VGS, GATE TO SOURCE VOLTAGE (V) Figure 5. Transfer Characteristics. 3 0 0.2 0.4 0.6 0.8 1 1.2 VSD, BODY DIODE FORWARD VOLTAGE (V) Figure 6. Body Diode Forward Voltage Variation with Source Current and Temperature. BSS123 Rev G(W) BSS123 Typical Characteristics 100 ID = 0.17A f = 1 MHz VGS = 0 V VDS = 30V 50V CISS 80 8 70V CAPACITANCE (pF) VGS, GATE-SOURCE VOLTAGE (V) 10 6 4 60 40 20 2 COSS CRSS 0 0 0 0.4 0.8 1.2 1.6 0 2 20 Qg, GATE CHARGE (nC) Figure 7. Gate Charge Characteristics. RDS(ON) LIMIT ID, DRAIN CURRENT (A) 10ms 100ms 1s 10s DC 0.01 VGS = 10V SINGLE PULSE RθJA = 350oC/W TA = 25oC 0.001 1 10 100 100 1000 SINGLE PULSE RθJA = 350°C/W TA = 25°C 4 3 2 1 0 0.001 0.01 0.1 1 VDS, DRAIN-SOURCE VOLTAGE (V) 10 100 1000 t1, TIME (sec) Figure 9. Maximum Safe Operating Area. r(t), NORMALIZED EFFECTIVE TRANSIENT THERMAL RESISTANCE 80 5 100µs 1ms 0.1 60 Figure 8. Capacitance Characteristics. P(pk), PEAK TRANSIENT POWER (W) 1 40 VDS, DRAIN TO SOURCE VOLTAGE (V) Figure 10. Single Pulse Maximum Power Dissipation. 1 D = 0.5 RθJA(t) = r(t) * RθJA o 0.2 0.1 RθJA = 350 C/W 0.1 0.05 P(pk) 0.02 0.01 t1 t2 TJ - TA = P * RθJA(t) Duty Cycle, D = t1 / t2 0.01 SINGLE PULSE 0.001 0.0001 0.001 0.01 0.1 1 10 100 1000 t1, TIME (sec) Figure 11. Transient Thermal Response Curve. Thermal characterization performed using the conditions described in Note 1a. Transient thermal response will change depending on the circuit board design. BSS123 Rev G(W) TRADEMARKS The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks. ACEx™ FACT™ ActiveArray™ FACT Quiet Series™ Bottomless™ FASTâ CoolFET™ FASTr™ CROSSVOLT™ FRFET™ DOME™ GlobalOptoisolator™ EcoSPARK™ GTO™ E2CMOSTM HiSeC™ EnSignaTM I2C™ Across the board. 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PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Product Status Definition Advance Information Formative or In Design This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. Preliminary First Production This datasheet contains preliminary data, and supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. No Identification Needed Full Production This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. Obsolete Not In Production This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor. The datasheet is printed for reference information only. Rev. I2 www.s-manuals.com