Features
• Compatible with MCS-51™ Products
• 2K Bytes of Reprogrammable Flash Memory
•
•
•
•
•
•
•
•
•
•
•

– Endurance: 1,000 Write/Erase Cycles
2.7V to 6V Operating Range
Fully Static Operation: 0 Hz to 24 MHz
Two-level Program Memory Lock
128 x 8-bit Internal RAM
15 Programmable I/O Lines
Two 16-bit Timer/Counters
Six Interrupt Sources
Programmable Serial UART Channel
Direct LED Drive Outputs
On-chip Analog Comparator
Low-power Idle and Power-down Modes

Description
The AT89C2051 is a low-voltage, high-performance CMOS 8-bit microcomputer with
2K bytes of Flash programmable and erasable read only memory (PEROM). The
device is manufactured using Atmel’s high-density nonvolatile memory technology
and is compatible with the industry-standard MCS-51 instruction set. By combining a
versatile 8-bit CPU with Flash on a monolithic chip, the Atmel AT89C2051 is a powerful microcomputer which provides a highly-flexible and cost-effective solution to many
embedded control applications.

8-bit
Microcontroller
with 2K Bytes
Flash
AT89C2051

The AT89C2051 provides the following standard features: 2K bytes of Flash, 128
bytes of RAM, 15 I/O lines, two 16-bit timer/counters, a five vector two-level interrupt
architecture, a full duplex serial port, a precision analog comparator, on-chip oscillator
and clock circuitry. In addition, the AT89C2051 is designed with static logic for operation down to zero frequency and supports two software selectable power saving
modes. The Idle Mode stops the CPU while allowing the RAM, timer/counters, serial
port and interrupt system to continue functioning. The power-down mode saves the
RAM contents but freezes the oscillator disabling all other chip functions until the next
hardware reset.

Pin Configuration
PDIP/SOIC
RST/VPP
(RXD) P3.0
(TXD) P3.1
XTAL2
XTAL1
(INT0) P3.2
(INT1) P3.3
(TO) P3.4
(T1) P3.5
GND

1
2
3
4
5
6
7
8
9
10

20
19
18
17
16
15
14
13
12
11

VCC
P1.7
P1.6
P1.5
P1.4
P1.3
P1.2
P1.1 (AIN1)
P1.0 (AIN0)
P3.7

Rev. 0368E–02/00

1

Block Diagram

2

AT89C2051

AT89C2051
Pin Description

Each machine cycle takes 12 oscillator or clock cycles.
XTAL1

VCC

Input to the inverting oscillator amplifier and input to the
internal clock operating circuit.

Supply voltage.
GND

XTAL2

Ground.

Output from the inverting oscillator amplifier.

Port 1
Port 1 is an 8-bit bi-irectional I/O port. Port pins P1.2 to
P1.7 provide internal pullups. P1.0 and P1.1 require external pullups. P1.0 and P1.1 also serve as the positive input
(AIN0) and the negative input (AIN1), respectively, of the
on-chip precision analog comparator. The Port 1 output
buffers can sink 20 mA and can drive LED displays directly.
When 1s are written to Port 1 pins, they can be used as
inputs. When pins P1.2 to P1.7 are used as inputs and are
externally pulled low, they will source current (IIL) because
of the internal pullups.

Oscillator Characteristics

Port 1 also receives code data during Flash programming
and verification.

XTAL1 and XTAL2 are the input and output, respectively,
of an inverting amplifier which can be configured for use as
an on-chip oscillator, as shown in Figure 1. Either a quartz
crystal or ceramic resonator may be used. To drive the
device from an external clock source, XTAL2 should be left
unconnected while XTAL1 is driven as shown in Figure 2.
There are no requirements on the duty cycle of the external
clock signal, since the input to the internal clocking circuitry
is through a divide-by-two flip-flop, but minimum and maximum voltage high and low time specifications must be
observed.

Port 3

Figure 1. Oscillator Connections

Port 3 pins P3.0 to P3.5, P3.7 are seven bi-irectional I/O
pins with internal pullups. P3.6 is hard-wired as an input to
the output of the on-chip comparator and is not accessible
as a general purpose I/O pin. The Port 3 output buffers can
sink 20 mA. When 1s are written to Port 3 pins they are
pulled high by the internal pullups and can be used as
inputs. As inputs, Port 3 pins that are externally being
pulled low will source current (IIL) because of the pullups.
Port 3 also serves the functions of various special features
of the AT89C2051 as listed below:
Port Pin

Alternate Functions

P3.0

RXD (serial input port)

P3.1

TXD (serial output port)

P3.2

INT0 (external interrupt 0)

P3.3

INT1 (external interrupt 1)

P3.4

T0 (timer 0 external input)

P3.5

T1 (timer 1 external input)

Note:

C1, C2 = 30 pF ± 10 pF for Crystals
= 40 pF ± 10 pF for Ceramic Resonators

Figure 2. External Clock Drive Configuration

Port 3 also receives some control signals for Flash programming and verification.
RST
Reset input. All I/O pins are reset to 1s as soon as RST
goes high. Holding the RST pin high for two machine
cycles while the oscillator is running resets the device.
3

Special Function Registers
A map of the on-chip memory area called the Special Function Register (SFR) space is shown in the table below.

random data, and write accesses will have an indeterminate effect.

Note that not all of the addresses are occupied, and unoccupied addresses may not be implemented on the chip.
Read accesses to these addresses will in general return

User software should not write 1s to these unlisted locations, since they may be used in future products to invoke
new features. In that case, the reset or inactive values of
the new bits will always be 0.

Table 1. AT89C2051 SFR Map and Reset Values
0F8H
0F0H

0FFH
B
00000000

0F7H

0E8H
0E0H

0EFH
ACC
00000000

0E7H

0D8H
0D0H

0DFH
PSW
00000000

0D7H

0C8H

0CFH

0C0H

0C7H

0B8H

IP
XXX00000

0BFH

0B0H

P3
11111111

0B7H

0A8H

IE
0XX00000

0AFH

0A0H
98H

SCON
00000000

90H

P1
11111111

88H

TCON
00000000

80H

4

0A7H
SBUF
XXXXXXXX

9FH
97H

TMOD
00000000

TL0
00000000

TL1
00000000

SP
00000111

DPL
00000000

DPH
00000000

AT89C2051

TH0
00000000

TH1
00000000

8FH
PCON
0XXX0000

87H

AT89C2051
Restrictions on Certain Instructions

Program Memory Lock Bits

The AT89C2051 and is an economical and cost-effective
member of Atmel’s growing family of microcontrollers. It
contains 2K bytes of flash program memory. It is fully compati bl e with the MCS-51 arc hitec tur e, and c an be
programmed using the MCS-51 instruction set. However,
there are a few considerations one must keep in mind
when utilizing certain instructions to program this device.

On the chip are two lock bits which can be left unprogrammed (U) or can be programmed (P) to obtain the
additional features listed in the table below:

All the instructions related to jumping or branching should
be restricted such that the destination address falls within
the physical program memory space of the device, which is
2K for the AT89C2051. This should be the responsibility of
the software programmer. For example, LJMP 7E0H
would be a valid instruction for the AT89C2051 (with 2K of
memory), whereas LJMP 900H would not.
1. Branching instructions:
LCALL, LJMP, ACALL, AJMP, SJMP, JMP @A+DPTR
These unconditional branching instructions will execute
correctly as long as the programmer keeps in mind that the
destination branching address must fall within the physical
boundaries of the program memory size (locations 00H to
7FFH for the 89C2051). Violating the physical space limits
may cause unknown program behavior.
CJNE [...], DJNZ [...], JB, JNB, JC, JNC, JBC, JZ, JNZ With
these conditional branching instructions the same rule
above applies. Again, violating the memory boundaries
may cause erratic execution.
For applications involving interrupts the normal interrupt
service routine address locations of the 80C51 family architecture have been preserved.
2. MOVX-related instructions, Data Memory:
The AT89C2051 contains 128 bytes of internal data memory. Thus, in the AT89C2051 the stack depth is limited to
128 bytes, the amount of available RAM. External DATA
memory access is not supported in this device, nor is external PROGRAM memory execution. Therefore, no MOVX
[...] instructions should be included in the program.
A typical 80C51 assembler will still assemble instructions,
even if they are written in violation of the restrictions mentioned above. It is the responsibility of the controller user to
know the physical features and limitations of the device
being used and adjust the instructions used
correspondingly.

Lock Bit Protection Modes(1)
Program Lock Bits
LB1

LB2

1

U

U

No program lock features.

2

P

U

Further programming of the Flash
is disabled.

3

P

P

Same as mode 2, also verify is
disabled.

Note:

Protection Type

1. The Lock Bits can only be erased with the Chip Erase
operation.

Idle Mode
In idle mode, the CPU puts itself to sleep while all the onchip peripherals remain active. The mode is invoked by
software. The content of the on-chip RAM and all the special functions registers remain unchanged during this
mode. The idle mode can be terminated by any enabled
interrupt or by a hardware reset.
P1.0 and P1.1 should be set to “0” if no external pullups are
used, or set to “1” if external pullups are used.
It should be noted that when idle is terminated by a hardware reset, the device normally resumes program
execution, from where it left off, up to two machine cycles
before the internal reset algorithm takes control. On-chip
hardware inhibits access to internal RAM in this event, but
access to the port pins is not inhibited. To eliminate the
possibility of an unexpected write to a port pin when Idle is
terminated by reset, the instruction following the one that
invokes Idle should not be one that writes to a port pin or to
external memory.

Power-down Mode
In the power down mode the oscillator is stopped, and the
instruction that invokes power down is the last instruction
executed. The on-chip RAM and Special Function Registers retain their values until the power down mode is
terminated. The only exit from power down is a hardware
reset. Reset redefines the SFRs but does not change the
on-chip RAM. The reset should not be activated before VCC
is restored to its normal operating level and must be held
active long enough to allow the oscillator to restart and
stabilize.
P1.0 and P1.1 should be set to “0” if no external pullups are
used, or set to “1” if external pullups are used.
5

Programming The Flash
The AT89C2051 is shipped with the 2K bytes of on-chip
PEROM code memory array in the erased state (i.e., contents = FFH) and ready to be programmed. The code
memory array is programmed one byte at a time. Once the
array is programmed, to re-program any non-blank byte,
the entire memory array needs to be erased electrically.
Internal Address Counter: The AT89C2051 contains an
internal PEROM address counter which is always reset to
000H on the rising edge of RST and is advanced by applying a positive going pulse to pin XTAL1.
Programming Algorithm: To program the AT89C2051,
the following sequence is recommended.
1. Power-up sequence:
Apply power between VCC and GND pins
Set RST and XTAL1 to GND
2. Set pin RST to “H”
Set pin P3.2 to “H”
3. Apply the appropriate combination of “H” or “L” logic
levels to pins P3.3, P3.4, P3.5, P3.7 to select one of the
programming operations shown in the PEROM Programming Modes table.
To Program and Verify the Array:
4. Apply data for Code byte at location 000H to P1.0 to
P1.7.
5. Raise RST to 12V to enable programming.
6. Pulse P3.2 once to program a byte in the PEROM array
or the lock bits. The byte-write cycle is self-timed and
typically takes 1.2 ms.
7. To verify the programmed data, lower RST from 12V to
logic “H” level and set pins P3.3 to P3.7 to the appropiate
levels. Output data can be read at the port P1 pins.
8. To program a byte at the next address location, pulse
XTAL1 pin once to advance the internal address
counter. Apply new data to the port P1 pins.
9. Repeat steps 5 through 8, changing data and advancing
the address counter for the entire 2K bytes array or until
the end of the object file is reached.
10.Power-off sequence:
set XTAL1 to “L”
set RST to “L”
Turn VCC power off
Data Polling: The AT89C2051 features Data Polling to
indicate the end of a write cycle. During a write cycle, an
attempted read of the last byte written will result in the complement of the written data on P1.7. Once the write cycle
has been completed, true data is valid on all outputs, and

6

AT89C2051

the next cycle may begin. Data Polling may begin any time
after a write cycle has been initiated.
Ready/Busy: The Progress of byte programming can also
be monitored by the RDY/BSY output signal. Pin P3.1 is
pulled low after P3.2 goes High during programming to indicate BUSY. P3.1 is pulled High again when programming is
done to indicate READY.
Program Verify: If lock bits LB1 and LB2 have not been
programmed code data can be read back via the data lines
for verification:
1. Reset the internal address counter to 000H by bringing
RST from “L” to “H”.
2. Apply the appropriate control signals for Read Code data
and read the output data at the port P1 pins.
3. Pulse pin XTAL1 once to advance the internal address
counter.
4. Read the next code data byte at the port P1 pins.
5. Repeat steps 3 and 4 until the entire array is read.
The lock bits cannot be verified directly. Verification of the
lock bits is achieved by observing that their features are
enabled.
Chip Erase: The entire PEROM array (2K bytes) and the
two Lock Bits are erased electrically by using the proper
combination of control signals and by holding P3.2 low for
10 ms. The code array is written with all “1”s in the Chip
Erase operation and must be executed before any nonblank memory byte can be re-programmed.
Reading the Signature Bytes: The signature bytes are
read by the same procedure as a normal verification of
locations 000H, 001H, and 002H, except that P3.5 and
P3.7 must be pulled to a logic low. The values returned are
as follows.
(000H) = 1EH indicates manufactured by Atmel
(001H) = 21H indicates 89C2051

Programming Interface
Every code byte in the Flash array can be written and the
entire array can be erased by using the appropriate combination of control signals. The write operation cycle is selftimed and once initiated, will automatically time itself to
completion.
All major programming vendors offer worldwide support for
the Atmel microcontroller series. Please contact your local
programming vendor for the appropriate software revision.

AT89C2051
Flash Programming Modes
Mode

RST/VPP

Write Code Data

(1)(3)

12V

Read Code Data(1)
Write Lock

H

H

P3.3

P3.4

P3.5

P3.7

L

H

H

H

L

L

H

H

Bit - 1

12V

H

H

H

H

Bit - 2

12V

H

H

L

L

H

L

L

L

L

L

L

L

Chip Erase

Read Signature Byte
Notes:

P3.2/PROG

12V

(2)

H

H

1. The internal PEROM address counter is reset to 000H on the rising edge of RST and is advanced by a positive pulse at
XTAL 1 pin.
2. Chip Erase requires a 10 ms PROG pulse.
3. P3.1 is pulled Low during programming to indicate RDY/BSY.

Figure 3. Programming the Flash Memory

Figure 4. Verifying the Flash Memory

PP

7

Flash Programming and Verification Characteristics
TA = 0°C to 70°C, VCC = 5.0 ± 10%
Symbol

Parameter

Min

Max

Units

VPP

Programming Enable Voltage

11.5

12.5

V

IPP

Programming Enable Current

250

µA

tDVGL

Data Setup to PROG Low

1.0

µs

tGHDX

Data Hold after PROG

1.0

µs

tEHSH

P3.4 (ENABLE) High to VPP

1.0

µs

tSHGL

VPP Setup to PROG Low

10

µs

tGHSL

VPP Hold after PROG

10

µs

tGLGH

PROG Width

1

tELQV

ENABLE Low to Data Valid

tEHQZ

Data Float after ENABLE

tGHBL

110

µs

1.0

µs

1.0

µs

PROG High to BUSY Low

50

ns

tWC

Byte Write Cycle Time

2.0

ms

tBHIH

RDY/BSY\ to Increment Clock Delay

tIHIL
Note:

1.

Increment Clock High
Only used in 12-volt programming mode.

Flash Programming and Verification Waveforms

8

AT89C2051

0

1.0

µs

200

ns

AT89C2051
Absolute Maximum Ratings*
Operating Temperature ................................. -55°C to +125°C

*NOTICE:

Storage Temperature ..................................... -65°C to +150°C
Voltage on Any Pin
with Respect to Ground .....................................-1.0V to +7.0V
Maximum Operating Voltage ............................................ 6.6V

Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.

DC Output Current...................................................... 25.0 mA

DC Characteristics
TA = -40°C to 85°C, VCC = 2.0V to 6.0V (unless otherwise noted)
Symbol

Parameter

Condition

VIL

Input Low-voltage

VIH

Input High-voltage

(Except XTAL1, RST)

VIH1

Input High-voltage

(XTAL1, RST)

VOL

Output Low-voltage(1)
(Ports 1, 3)

IOL = 20 mA, VCC = 5V
IOL = 10 mA, VCC = 2.7V

VOH

Output High-voltage
(Ports 1, 3)

IOH = -80 µA, VCC = 5V ± 10%

Min

Max

Units

-0.5

0.2 VCC - 0.1

V

0.2 VCC + 0.9

VCC + 0.5

V

0.7 VCC

VCC + 0.5

V

0.5

V

2.4

V

IOH = -30 µA

0.75 VCC

V

IOH = -12 µA

0.9 VCC

V

IIL

Logical 0 Input Current
(Ports 1, 3)

VIN = 0.45V

-50

µA

ITL

Logical 1 to 0 Transition Current
(Ports 1, 3)

VIN = 2V, VCC = 5V ± 10%

-750

µA

ILI

Input Leakage Current
(Port P1.0, P1.1)

0 < VIN < VCC

±10

µA

VOS

Comparator Input Offset Voltage

VCC = 5V

20

mV

VCM

Comparator Input Common
Mode Voltage

0

VCC

V

RRST

Reset Pull-down Resistor

50

300

KΩ

CIO

Pin Capacitance

Test Freq. = 1 MHz, TA = 25°C

10

pF

ICC

Power Supply Current

Active Mode, 12 MHz, VCC = 6V/3V

15/5.5

mA

Idle Mode, 12 MHz, VCC = 6V/3V
P1.0 & P1.1 = 0V or VCC

5/1

mA

VCC = 6V P1.0 & P1.1 = 0V or VCC

100

µA

Power-down Mode(2)
Notes:

VCC = 3V P1.0 & P1.1 = 0V or VCC
20
µA
1. Under steady state (non-transient) conditions, IOL must be externally limited as follows:
Maximum IOL per port pin: 20 mA
Maximum total IOL for all output pins: 80 mA
If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater
than the listed test conditions.
2. Minimum VCC for Power-down is 2V.

9

External Clock Drive Waveforms

External Clock Drive
VCC = 2.7V to 6.0V
Symbol

Parameter

1/tCLCL

Oscillator Frequency

tCLCL

Clock Period

tCHCX

VCC = 4.0V to 6.0V

Min

Max

Min

Max

0

12

0

24

Units
MHz

83.3

41.6

ns

High Time

30

15

ns

tCLCX

Low Time

30

15

ns

tCLCH

Rise Time

20

20

ns

tCHCL

Fall Time

20

20

ns

10

AT89C2051

AT89C2051
()

Serial Port Timing: Shift Register Mode Test Conditions
VCC = 5.0V ± 20%; Load Capacitance = 80 pF
12 MHz Osc
Max

Variable Oscillator

Symbol

Parameter

Min

Min

tXLXL

Serial Port Clock Cycle Time

1.0

12tCLCL

µs

tQVXH

Output Data Setup to Clock Rising Edge

700

10tCLCL-133

ns

tXHQX

Output Data Hold after Clock Rising Edge

50

2tCLCL-117

ns

tXHDX

Input Data Hold after Clock Rising Edge

0

0

ns

tXHDV

Clock Rising Edge to Input Data Valid

700

Max

10tCLCL-133

Units

ns

Shift Register Mode Timing Waveforms

AC Testing Input/Output Waveforms(1)

Float Waveforms(1)

Note:

Note:

1. AC Inputs during testing are driven at VCC - 0.5V for a
logic 1 and 0.45V for a logic 0. Timing measurements
are made at VIH min. for a logic 1 and VIL max. for a
logic 0.

1. For timing purposes, a port pin is no longer floating
when a 100 mV change from load voltage occurs. A
port pin begins to float when 100 mV change frothe
loaded VOH/VOL level occurs.

11

AT89C2051
TYPICAL ICC - ACTIVE (85°C)
20
Vcc=6.0V

I 15
C
C 10
m
A

Vcc=5.0V
Vcc=3.0V

5

0
0

6

12

18

24

FREQUENCY (MHz)

AT89C2051
TYPICAL ICC - IDLE (85°C)
3
Vcc=6.0V

I
C 2
C

Vcc=5.0V

m 1
A
Vcc=3.0V
0
0

3

6

9

12

FREQUENCY (MHz)

AT89C2051
TYPICAL ICC vs. VOLTAGE- POWER DOWN (85°C)
20

I 15
C
C 10
µ
A

5

0
3.0V

4.0V

5.0V

Vcc VOLTAGE

Notes:

12

1. XTAL1 tied to GND for ICC (power-down)
2. P.1.0 and P1.1 = VCC or GND
3. Lock bits programmed

AT89C2051

6.0V

AT89C2051
Ordering Information
Speed
(MHz)

Power
Supply

12

2.7V to 6.0V

24

4.0V to 6.0V

Ordering Code

Package

Operation Range

AT89C2051-12PC
AT89C2051-12SC

20P3
20S

Commercial
(0°C to 70°C)

AT89C2051-12PI
AT89C2051-12SI

20P3
20S

Industrial
(-40°C to 85°C)

AT89C2051-24PC
AT89C2051-24SC

20P3
20S

Commercial
(0°C to 70°C)

AT89C2051-24PI
AT89C2051-24SI

20P3
20S

Industrial
(-40°C to 85°C)

Package Type
20P3

20-lead, 0.300” Wide, Plastic Dual In-line Package (PDIP)

20S

20-lead, 0.300” Wide, Plastic Gull Wing Small Outline (SOIC)

13

Packaging Information
20P3, 20-lead, 0.300" Wide, Plastic Dual Inline
Package (PDIP)
Dimensions in Inches and (Millimeters)

20S, 20-lead, 0.300" Wide, Plastic Gull WIng Small
Outline (SOIC)
Dimensions in Inches and (Millimeters)

JEDEC STANDARD MS-001 AD
1.060(26.9)
.980(24.9)

0.020 (0.508)
0.013 (0.330)

PIN
1

.280(7.11)
.240(6.10)

0.299 (7.60) 0.420 (10.7)
0.291 (7.39) 0.393 (9.98)
PIN 1

.090(2.29)
MAX

.900(22.86) REF

.050 (1.27) BSC

.210(5.33)
MAX

.005(.127)
MIN

SEATING
PLANE

.110(2.79)
.090(2.29)

.070(1.78)
.045(1.13)

0 REF
15
.430(10.92) MAX

14

0.105 (2.67)
0.092 (2.34)

.022(.559)
.014(.356)

.325(8.26)
.300(7.62)
.014(.356)
.008(.203)

0.513 (13.0)
0.497 (12.6)

.015(.381) MIN

.150(3.81)
.115(2.92)

AT89C2051

0.012 (0.305)
0.003 (0.076)

0
REF
8

0.013 (0.330)
0.009 (0.229)

0.035 (0.889)
0.015 (0.381)

Atmel Headquarters

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