INTEGRATED CIRCUITS

DATA SHEET
For a complete data sheet, please also download:
• The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
• The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
• The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines

74HC/HCT193
Presettable synchronous 4-bit
binary up/down counter
Product specification
File under Integrated Circuits, IC06

December 1990

Philips Semiconductors

Product specification

Presettable synchronous 4-bit binary
up/down counter

One clock should be held HIGH while counting with the
other, otherwise the circuit will either count by two’s or not
at all, depending on the state of the first flip-flop, which
cannot toggle as long as either clock input is LOW.
Applications requiring reversible operation must make the
reversing decision while the activating clock is HIGH to
avoid erroneous counts.

FEATURES
• Synchronous reversible 4-bit binary counting
• Asynchronous parallel load
• Asynchronous reset
• Expandable without external logic
• Output capability: standard

The terminal count up (TCU) and terminal count down
(TCD) outputs are normally HIGH. When the circuit has
reached the maximum count state of 15, the next
HIGH-to-LOW transition of CPU will cause TCU to go
LOW.

• ICC category: MSI
GENERAL DESCRIPTION
The 74HC/HCT193 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.

TCU will stay LOW until CPU goes HIGH again, duplicating
the count up clock.
Likewise, the TCD output will go LOW when the circuit is in
the zero state and the CPD goes LOW. The terminal count
outputs can be used as the clock input signals to the next
higher order circuit in a multistage counter, since they
duplicate the clock waveforms. Multistage counters will not
be fully synchronous, since there is a slight delay time
difference added for each stage that is added.

The 74HC/HCT193 are 4-bit synchronous binary up/down
counters. Separate up/down clocks, CPU and
CPD respectively, simplify operation. The outputs change
state synchronously with the LOW-to-HIGH transition of
either clock input. If the CPU clock is pulsed while CPD is
held HIGH, the device will count up. If the CPD clock is
pulsed while CPU is held HIGH, the device will count down.
Only one clock input can be held HIGH at any time, or
erroneous operation will result. The device can be cleared
at any time by the asynchronous master reset input (MR);
it may also be loaded in parallel by activating the
asynchronous parallel load input (PL).

The counter may be preset by the asynchronous parallel
load capability of the circuit. Information present on the
parallel data inputs (D0 to D3) is loaded into the counter
and appears on the outputs (Q0 to Q3) regardless of the
conditions of the clock inputs when the parallel load
(PL) input is LOW. A HIGH level on the master reset (MR)
input will disable the parallel load gates, override both
clock inputs and set all outputs (Q0 to Q3) LOW. If one of
the clock inputs is LOW during and after a reset or load
operation, the next LOW-to-HIGH transition of that clock
will be interpreted as a legitimate signal and will be
counted.

The “193” contains four master-slave JK flip-flops with the
necessary steering logic to provide the asynchronous
reset, load, and synchronous count up and count down
functions.
Each flip-flop contains JK feedback from slave to master,
such that a LOW-to-HIGH transition on the CPD input will
decrease the count by one, while a similar transition on the
CPU input will advance the count by one.

December 1990

74HC/HCT193

2

Philips Semiconductors

Product specification

Presettable synchronous 4-bit binary
up/down counter

74HC/HCT193

QUICK REFERENCE DATA
GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns
TYPICAL
SYMBOL

PARAMETER

CONDITIONS

UNIT
HC

tPHL/ tPLH

propagation delay CPD, CPU to Qn

fmax

maximum clock frequency

CI

input capacitance

CPD

power dissipation capacitance per package

CL = 15 pF; VCC = 5 V

notes 1 and 2

Notes
1. CPD is used to determine the dynamic power dissipation (PD in µW):
PD = CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) where:
fi = input frequency in MHz
fo = output frequency in MHz
∑ (CL × VCC2 × fo) = sum of outputs
CL = output load capacitance in pF
VCC = supply voltage in V
2. For HC the condition is VI = GND to VCC
For HCT the condition is VI = GND to VCC − 1.5 V
ORDERING INFORMATION
See “74HC/HCT/HCU/HCMOS Logic Package Information”.

December 1990

3

HCT

20

20

ns

45

47

MHz

3.5

3.5

pF

24

26

pF

Philips Semiconductors

Product specification

Presettable synchronous 4-bit binary
up/down counter

74HC/HCT193

PIN DESCRIPTION
PIN NO.

SYMBOL

NAME AND FUNCTION

3, 2, 6, 7

Q0 to Q3

flip-flop outputs

4

CPD

count down clock input(1)

5

CPU

count up clock input(1)

8

GND

ground (0 V)

11

PL

asynchronous parallel load input (active LOW)

12

TCU

terminal count up (carry) output (active LOW)

13

TCD

terminal count down (borrow) output (active LOW)

14

MR

asynchronous master reset input (active HIGH)

15, 1, 10, 9

D0 to D3

data inputs

16

VCC

positive supply voltage

Note
1. LOW-to-HIGH, edge triggered

Fig.1 Pin configuration.

Fig.2 Logic symbol.

Fig.3 IEC logic symbol.

December 1990

4

Philips Semiconductors

Product specification

Presettable synchronous 4-bit binary
up/down counter

74HC/HCT193

FUNCTION TABLE
INPUTS

OUTPUTS

OPERATING MODE
MR

PL

CPU

CPD

D0

D1

D2

D3

Q0

Q1

Q2

Q3

TCU

TCD

reset (clear)

H
H

X
X

X
X

L
H

X
X

X
X

X
X

X
X

L
L

L
L

L
L

L
L

H
H

L
H

parallel load

L
L
L
L

L
L
L
L

X
X
L
H

L
H
X
X

L
L
H
H

L
L
H
H

L
L
H
H

L
L
H
H

L
L
H
H

L
L
H
H

L
L
H
H

L
L
H
H

H
H
L
H

L
H
H
H

count up

L

H

↑

H

X

X

X

X

count up

H(2)

H

count down

L

H

H

↑

X

X

X

X

count down

H

H(3)

Notes
1. H
L
X
↑

= HIGH voltage level
= LOW voltage level
= don’t care
= LOW-to-HIGH clock transition

2. TCU = CPU at terminal count up (HHHH)
3. TCD = CPD at terminal count down (LLLL)

Fig.4 Functional diagram.

December 1990

5

Philips Semiconductors

Product specification

Presettable synchronous 4-bit binary
up/down counter

74HC/HCT193

(1) Clear overrides load, data and
count inputs.
(2) When counting up the count down
clock input (CPD) must be HIGH,
when counting down the count up
clock input (CPU) must be HIGH.
Sequence
Clear (reset outputs to zero);
load (preset) to binary thirteen;
count up to fourteen, fifteen,
terminal count up, zero, one
and two;
count down to one, zero,
terminal count down, fifteen,

Fig.5 Typical clear, load and count sequence.

Fig.6 Logic diagram.
December 1990

6

Philips Semiconductors

Product specification

Presettable synchronous 4-bit binary
up/down counter

74HC/HCT193

DC CHARACTERISTICS FOR 74HC
For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”.
Output capability: standard
ICC category: MSI
AC CHARACTERISTICS FOR 74HC
GND = 0 V; tr = tf = 6 ns; CL = 50 pF
Tamb (°C)

TEST CONDITIONS

74HC
SYMBOL PARAMETER

+25

−40 to +85

min. typ. max. min.

max.

−40 to +125

UNIT V
WAVEFORMS
CC
(V)

min. max.

tPHL/ tPLH

propagation delay
CPU, CPD to Qn

63
23
18

215
43
37

270
54
46

325
65
55

ns

2.0
4.5
6.0

Fig.7

tPHL/ tPLH

propagation delay
CPU to TCU

39
14
11

125
25
21

155
31
26

190
38
32

ns

2.0
4.5
6.0

Fig.8

tPHL/ tPLH

propagation delay
CPD to TCD

39
14
11

125
25
21

155
31
26

190
38
32

ns

2.0
4.5
6.0

Fig.8

tPHL/ tPLH

propagation delay
PL to Qn

69
25
20

220
44
37

275
55
47

330
66
56

ns

2.0
4.5
6.0

Fig.9

tPHL

propagation delay
MR to Qn

58
21
17

200
40
34

250
50
43

300
60
51

ns

2.0
4.5
6.0

Fig.10

tPHL/ tPLH

propagation delay
Dn to Qn

69
25
20

210
42
36

265
53
45

315
63
54

ns

2.0
4.5
6.0

Fig.9

tPHL/ tPLH

propagation delay
PL to TCU, PL to TCD

80
29
23

290
58
49

365
73
62

435
87
74

ns

2.0
4.5
6.0

Fig.12

tPHL/ tPLH

propagation delay
MR to TCU, MR to TCD

74
27
22

285
57
48

355
71
60

430
86
73

ns

2.0
4.5
6.0

Fig.12

tPHL/ tPLH

propagation delay
Dn to TCU, Dn to TCD

80
29
23

290
58
49

365
73
62

435
87
74

ns

2.0
4.5
6.0

Fig.12

tTHL/ tTLH

output transition time

19
7
6

75
15
13

95
19
16

110
22
19

ns

2.0
4.5
6.0

Fig.10

tW

up, down clock pulse
width HIGH or LOW

ns

2.0
4.5
6.0

Fig.7

December 1990

100
20
17

22
8
6

125
25
21

7

150
30
26

Philips Semiconductors

Product specification

Presettable synchronous 4-bit binary
up/down counter

74HC/HCT193

Tamb (°C)

TEST CONDITIONS

74HC
SYMBOL PARAMETER

+25

−40 to +85

min. typ. max. min.

max.

−40 to +125

WAVEFORMS
UNIT V
CC
(V)

min. max.

tW

master reset pulse width
HIGH

100
20
17

25
9
7

125
25
21

150
30
26

ns

2.0
4.5
6.0

Fig.10

tW

parallel load pulse width
LOW

100
20
17

19
7
6

125
25
21

150
30
26

ns

2.0
4.5
6.0

Fig.9

trem

removal time
PL to CPU, CPD

50
10
9

8
3
2

65
13
11

75
15
13

ns

2.0
4.5
6.0

Fig.9

trem

removal time
MR to CPU, CPD

50
10
9

0
0
0

65
13
11

75
15
13

ns

2.0
4.5
6.0

Fig.10

tsu

set-up time
Dn to PL

80
16
14

22
8
6

100
20
17

120
24
20

ns

2.0
4.5
6.0

Fig.11 note:
CPU = CPD =
HIGH

th

hold time
Dn to PL

0
0
0

−14
−5
−4

0
0
0

0
0
0

ns

2.0
4.5
6.0

Fig.11

th

hold time
CPU to CPD,
CPD to CPU

80
16
8

22
8
6

100
20
17

120
24
20

ns

2.0
4.5
6.0

Fig.13

fmax

maximum up, down clock 4.0
pulse frequency
20
24

13.5
41
49

3.2
16
19

2.6
13
15

MHz

2.0
4.5
6.0

Fig.7

December 1990

8

Philips Semiconductors

Product specification

Presettable synchronous 4-bit binary
up/down counter

74HC/HCT193

DC CHARACTERISTICS FOR 74HCT
For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”.
Output capability: standard
ICC category: MSI
Note to HCT types
The value of additional quiescent supply current (∆ICC) for a unit load of 1 is given in the family specifications.
To determine ∆ICC per input, multiply this value by the unit load coefficient shown in the table below.

INPUT

UNIT LOAD COEFFICIENT

Dn
CPU, CPD
PL
MR

0.35
1.40
0.65
1.05

December 1990

9

Philips Semiconductors

Product specification

Presettable synchronous 4-bit binary
up/down counter

74HC/HCT193

AC CHARACTERISTICS FOR 74HCT
GND = 0 V; tr = tf = 6 ns; CL = 50 pF
Tamb (°C)

TEST CONDITIONS

74HCT
SYMBOL PARAMETER

+25
min.

−40 to +85

−40 to +125

typ.

max. min. max. min. max.

WAVEFORMS
UNIT V
CC
(V)

tPHL/ tPLH

propagation delay
CPU, CPD to Qn

23

43

54

65

ns

4.5

Fig.7

tPHL/ tPLH

propagation delay
CPU to TCU

15

27

34

41

ns

4.5

Fig.8

tPHL/ tPLH

propagation delay
CPD to TCD

15

27

34

41

ns

4.5

Fig.8

tPHL/ tPLH

propagation delay
PL to Qn

26

46

58

69

ns

4.5

Fig.9

tPHL

propagation delay
MR to Qn

22

40

50

60

ns

4.5

Fig.10

tPHL/ tPLH

propagation delay
Dn to Qn

27

46

58

69

ns

4.5

Fig.9

tPHL/ tPLH

propagation delay
PL to TCU, PL to TCD

31

55

69

83

ns

4.5

Fig.12

tPHL/ tPLH

propagation delay
MR to TCU, MR to TCD

29

55

69

83

ns

4.5

Fig.12

tPHL/ tPLH

propagation delay
Dn to TCU, Dn to TCD

32

58

73

87

ns

4.5

Fig.12

tTHL/ tTLH

output transition time

7

15

19

22

ns

4.5

Fig.10

tW

up, down clock pulse width
HIGH or LOW

25

11

31

38

ns

4.5

Fig.7

tW

master reset pulse width
HIGH

20

7

25

30

ns

4.5

Fig.10

tW

parallel load pulse width
LOW

20

8

25

30

ns

4.5

Fig.9

trem

removal time
PL to CPU, CPD

10

2

13

15

ns

4.5

Fig.9

trem

removal time
MR to CPU, CPD

10

0

13

15

ns

4.5

Fig.10

tsu

set-up time
Dn to PL

16

8

20

24

ns

4.5

Fig.11 note:
CPU = CPD =
HIGH

th

hold time
Dn to PL

0

−6

0

0

ns

4.5

Fig.11

th

hold time
CPU to CPD, CPD to CPU

16

7

20

24

ns

4.5

Fig.13

fmax

maximum up, down clock
pulse frequency

20

43

16

13

MHz

4.5

Fig.7

December 1990

10

Philips Semiconductors

Product specification

Presettable synchronous 4-bit binary
up/down counter

74HC/HCT193

AC WAVEFORMS

(1) HC : VM = 50%; VI = GND to VCC.
HCT: VM = 1.3V; VI = GND to 3 V.

Fig.7

Waveforms showing the clock (CPU, CPD) to output (Qn) propagation delays, the clock pulse width, and
the maximum clock pulse frequency.

(1) HC : VM = 50%; VI = GND to VCC.
HCT: VM = 1.3V; VI = GND to 3 V.

Fig.8 Waveforms showing the clock (CPU, CPD) to terminal count output (TCU, TCD) propagation delays.

(1) HC : VM = 50%; VI = GND to VCC.
HCT: VM = 1.3V; VI = GND to 3 V.

Fig.9

Waveforms showing the parallel load input (PL) and data (Dn) to Qn output propagation delays and
PL removal time to clock input (CPU, CPD).

December 1990

11

Philips Semiconductors

Product specification

Presettable synchronous 4-bit binary
up/down counter

74HC/HCT193

(1) HC : VM = 50%; VI = GND to VCC.
HCT: VM = 1.3V; VI = GND to 3 V.

Fig.10 Waveforms showing the master reset input (MR) pulse width, MR to Qn propagation delays, MR to CPU,
CPD removal time and output transition times.

The shaded areas indicate when the input is permitted to
change for predictable output performance.
(1) HC : VM = 50%; VI = GND to VCC.
HCT: VM = 1.3V; VI = GND to 3 V.

Fig.11 Waveforms showing the data input (Dn) to parallel load input (PL) set-up and hold times.

(1) HC : VM = 50%; VI = GND to VCC.
HCT: VM = 1.3V; VI = GND to 3 V.

Fig.12 Waveforms showing the data input (Dn), parallel load input (PL) and the master reset input (MR) to the
terminal count outputs (TCU, TCD) propagation delays.

(1) HC : VM = 50%; VI = GND to VCC.
HCT: VM = 1.3V; VI = GND to 3 V.

Fig.13 Waveforms showing the CPU to CPD or CPD to CPU hold times.

December 1990

12

Philips Semiconductors

Product specification

Presettable synchronous 4-bit binary
up/down counter

74HC/HCT193

APPLICATION INFORMATION

Fig.14 Cascaded up/down counter with parallel load.

PACKAGE OUTLINES
See “74HC/HCT/HCU/HCMOS Logic Package Outlines”.

December 1990

13

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