MC74HC04A
Hex Inverter
High−Performance Silicon−Gate CMOS
The MC74HC04A is identical in pinout to the LS04 and the
MC14069. The device inputs are compatible with Standard CMOS
outputs; with pullup resistors, they are compatible with LSTTL
outputs.
The device consists of six three−stage inverters.

http://onsemi.com
MARKING
DIAGRAMS

Features

•
•
•
•
•
•
•
•

Output Drive Capability: 10 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS and TTL
Operating Voltage Range: 2.0 to 6.0 V
Low Input Current: 1 
A
High Noise Immunity Characteristic of CMOS Devices
In Compliance With the JEDEC Standard No. 7A Requirements
Chip Complexity: 36 FETs or 9 Equivalent Gates
Pb−Free Packages are Available*

14
PDIP−14
N SUFFIX
CASE 646

14
1

1
14
SOIC−14
D SUFFIX
CASE 751A

14
1

A2

1

2

3

4

HC04A
AWLYWW
1

LOGIC DIAGRAM
A1

MC74HC04AN
AWLYYWW

Y1

14
14

Y2

1

TSSOP−14
DT SUFFIX
CASE 948G

HC
04
ALYW
1

A3

5

6

Y3
A
= Assembly Location
WL or L = Wafer Lot
YY or Y = Year
WW or W = Work Week

Y=A
A4

A5

A6

9

8

11

10

13

12

Y4

Y5

FUNCTION TABLE
Y6

Pinout: 14−Lead Packages (Top View)
VCC

A6

Y6

A5

Y5

A4

Y4

14

13

12

11

10

9

8

Inputs

Outputs

A

Y

L
H

H
L

ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.

1

2

3

4

5

6

7

A1

Y1

A2

Y2

A3

Y3

GND

*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
 Semiconductor Components Industries, LLC, 2005

May, 2005 − Rev. 10

1

Publication Order Number:
MC74HC04A/D

MC74HC04A

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
MAXIMUM RATINGS
Symbol

Parameter

Value

Unit

– 0.5 to + 7.0

V

DC Input Voltage (Referenced to GND)

– 0.5 to VCC + 0.5

V

DC Output Voltage (Referenced to GND)

– 0.5 to VCC + 0.5

V

VCC

DC Supply Voltage (Referenced to GND)

Vin

Vout
Iin

DC Input Current, per Pin

± 20

mA

Iout

DC Output Current, per Pin

± 25

mA

ICC

DC Supply Current, VCC and GND Pins

± 50

mA

PD

Power Dissipation in Still Air,

750
500
450

mW

Tstg

Storage Temperature

– 65 to + 150


C

TL

Lead Temperature, 1 mm from Case for 10 Seconds
Plastic DIP, SOIC or TSSOP Package

Plastic DIP†
SOIC Package†
TSSOP Package†


C

260

Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit
values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied,
damage may occur and reliability may be affected.
*This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be
taken to avoid applications of any voltage higher than maximum rated voltages to this high−impedance circuit. For proper operation, Vin and
Vout should be constrained to the range GND 
 (Vin or Vout) 
 VCC. Unused inputs must always be tied to an appropriate logic voltage level
(e.g., either GND or VCC). Unused outputs must be left open.
†Derating − Plastic DIP: – 10 mW/
C from 65
 to 125
C
SOIC Package: – 7 mW/
C from 65
 to 125
C
TSSOP Package: − 6.1 mW/
C from 65
 to 125
C
For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High−Speed CMOS Data Book (DL129/D).

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
RECOMMENDED OPERATING CONDITIONS
Symbol
VCC

Vin, Vout

Parameter

Min

DC Supply Voltage (Referenced to GND)

DC Input Voltage, Output Voltage (Referenced to GND)

TA

Operating Temperature, All Package Types

tr, tf

Input Rise and Fall Time
(Figure 1)

VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V

Max

Unit

2.0

6.0

V

0

VCC

V

– 55

+ 125


C

0
0
0

1000
500
400

ns

ORDERING INFORMATION
Package

Shipping†

MC74HC04AN

PDIP−14

2000 / Rail

MC74HC04ANG

PDIP−14
(Pb−Free)

2000 / Rail

MC74HC04AD

SOIC−14

55 / Rail

MC74HC04ADG

SOIC−14
(Pb−Free)

55 / Rail

MC74HC04ADR2

SOIC−14

2500 / Tape & Reel

MC74HC04ADR2G

SOIC−14
(Pb−Free)

2500 / Tape & Reel

MC74HC04ADTR2

TSSOP−14*

2500 / Tape & Reel

MC74HC04AF

SOEIAJ−14

50 / Rail

MC74HC04AFG

SOEIAJ−14
(Pb−Free)

50 / Rail

MC74HC04AFEL

SOEIAJ−14

2000 / Tape & Reel

MC74HC04AFELG

SOEIAJ−14
(Pb−Free)

2000 / Tape & Reel

mber
Device Order N
Number

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*This package is inherently Pb−Free.

http://onsemi.com
2

MC74HC04A
DC CHARACTERISTICS (Voltages Referenced to GND)

Symbol

Parameter

Condition

Guaranteed Limit

VCC
V

−55 to 25°C

≤85°C

≤125°C

Unit

VIH

Minimum High−Level Input
Voltage

Vout = 0.1V or VCC −0.1V
|Iout| ≤ 20
A

2.0
3.0
4.5
6.0

1.50
2.10
3.15
4.20

1.50
2.10
3.15
4.20

1.50
2.10
3.15
4.20

V

VIL

Maximum Low−Level Input
Voltage

Vout = 0.1V or VCC − 0.1V
|Iout| ≤ 20
A

2.0
3.0
4.5
6.0

0.50
0.90
1.35
1.80

0.50
0.90
1.35
1.80

0.50
0.90
1.35
1.80

V

VOH

Minimum High−Level Output
Voltage

Vin = VIH or VIL
|Iout| ≤ 20
A

2.0
4.5
6.0

1.9
4.4
5.9

1.9
4.4
5.9

1.9
4.4
5.9

V

3.0
4.5
6.0

2.48
3.98
5.48

2.34
3.84
5.34

2.20
3.70
5.20

2.0
4.5
6.0

0.1
0.1
0.1

0.1
0.1
0.1

0.1
0.1
0.1

3.0
4.5
6.0

0.26
0.26
0.26

0.33
0.33
0.33

0.40
0.40
0.40

|Iout| ≤ 2.4mA
|Iout| ≤ 4.0mA
|Iout| ≤ 5.2mA

Vin =VIH or VIL

VOL

Maximum Low−Level Output
Voltage

Vin = VIH or VIL
|Iout| ≤ 20
A
|Iout| ≤ 2.4mA
|Iout| ≤ 4.0mA
|Iout| ≤ 5.2mA

Vin = VIH or VIL

V

Iin

Maximum Input Leakage
Current

Vin = VCC or GND

6.0

± 0.1

± 1.0

± 1.0


A

ICC

Maximum Quiescent Supply
Current (per Package)

Vin = VCC or GND
Iout = 0
A

6.0

1.0

10

40


A

NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High−Speed CMOS Data Book (DL129/D).

AC CHARACTERISTICS (CL = 50pF, Input tr = tf = 6ns)
Symbol

Parameter

Guaranteed Limit

VCC
V

−55 to 25°C

≤85°C

≤125°C

Unit

tPLH,
tPHL

Maximum Propagation Delay, Input A or B to Output Y
(Figures 1 and 2)

2.0
3.0
4.5
6.0

75
30
15
13

95
40
19
16

110
55
22
19

ns

tTLH,
tTHL

Maximum Output Transition Time, Any Output
(Figures 1 and 2)

2.0
3.0
4.5
6.0

75
27
15
13

95
32
19
16

110
36
22
19

ns

10

10

10

pF

Cin

Maximum Input Capacitance

NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the ON
Semiconductor High−Speed CMOS Data Book (DL129/D).
Typical @ 25°C, VCC = 5.0 V
CPD

20

Power Dissipation Capacitance (Per Inverter)*

* Used to determine the no−load dynamic power consumption: P D = CPD VCC
ON Semiconductor High−Speed CMOS Data Book (DL129/D).

2f

http://onsemi.com
3

pF

+ ICC VCC . For load considerations, see Chapter 2 of the

MC74HC04A
tf
INPUT A

tr
VCC

90%
50%
10%

GND

tPLH

tPHL
90%
50%
10%

OUTPUT Y

tTHL

tTLH

Figure 1. Switching Waveforms

TEST
POINT
OUTPUT
DEVICE
UNDER
TEST

CL*

*Includes all probe and jig capacitance

Figure 2. Test Circuit

A

Y

Figure 3. Expanded Logic Diagram
(1/6 of the Device Shown)

http://onsemi.com
4

MC74HC04A
PACKAGE DIMENSIONS
PDIP−14
N SUFFIX
CASE 646−06
ISSUE N

14

8

1

7

NOTES:
1. DIMENSIONING AND TOLERANCING
PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS
WHEN FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE
MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.

B

A
F

DIM
A
B
C
D
F
G
H
J
K
L
M
N

L

N

C

−T−
SEATING
PLANE

J

K
H

D 14 PL

G

M

0.13 (0.005)

M

INCHES
MIN
MAX
0.715
0.770
0.240
0.260
0.145
0.185
0.015
0.021
0.040
0.070
0.100 BSC
0.052
0.095
0.008
0.015
0.115
0.135
0.290
0.310
−−−
10 

0.015
0.039

MILLIMETERS
MIN
MAX
18.16
18.80
6.10
6.60
3.69
4.69
0.38
0.53
1.02
1.78
2.54 BSC
1.32
2.41
0.20
0.38
2.92
3.43
7.37
7.87
−−−
10 

0.38
1.01

SOIC−14
D SUFFIX
CASE 751A−03
ISSUE G

−A−
14

8

−B−

P 7 PL
0.25 (0.010)

M

B

M

7

1

G

F

R X 45 


C

−T−
SEATING
PLANE

D 14 PL
0.25 (0.010)

M

T B

J

M

K
S

A

S

http://onsemi.com
5

NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.127
(0.005) TOTAL IN EXCESS OF THE D
DIMENSION AT MAXIMUM MATERIAL
CONDITION.

DIM
A
B
C
D
F
G
J
K
M
P
R

MILLIMETERS
MIN
MAX
8.55
8.75
3.80
4.00
1.35
1.75
0.35
0.49
0.40
1.25
1.27 BSC
0.19
0.25
0.10
0.25
0

7

5.80
6.20
0.25
0.50

INCHES
MIN
MAX
0.337 0.344
0.150 0.157
0.054 0.068
0.014 0.019
0.016 0.049
0.050 BSC
0.008 0.009
0.004 0.009
0

7

0.228 0.244
0.010 0.019

MC74HC04A
PACKAGE DIMENSIONS
TSSOP−14
DT SUFFIX
CASE 948G−01
ISSUE A
14X K REF

0.10 (0.004)
0.15 (0.006) T U

M

T U

V

S

NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL
NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08
(0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.

S

S

N
2X

14

L/2

0.25 (0.010)

8

M
B
−U−

L
PIN 1
IDENT.

F
7

1

0.15 (0.006) T U

N

S

DETAIL E
K

A
−V−

ÉÉÉ
ÇÇÇ
ÇÇÇ
ÉÉÉ
ÇÇÇ
K1

J J1

SECTION N−N
−W−

C
0.10 (0.004)
−T− SEATING
PLANE

D

G

H

DETAIL E

DIM
A
B
C
D
F
G
H
J
J1
K
K1
L
M

MILLIMETERS
INCHES
MIN
MAX
MIN MAX
4.90
5.10 0.193 0.200
4.30
4.50 0.169 0.177
−−−
1.20
−−− 0.047
0.05
0.15 0.002 0.006
0.50
0.75 0.020 0.030
0.65 BSC
0.026 BSC
0.50
0.60 0.020 0.024
0.09
0.20 0.004 0.008
0.09
0.16 0.004 0.006
0.19
0.30 0.007 0.012
0.19
0.25 0.007 0.010
6.40 BSC
0.252 BSC
0

8

0

8


ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.

PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
Literature Distribution Center for ON Semiconductor
P.O. Box 61312, Phoenix, Arizona 85082−1312 USA
Phone: 480−829−7710 or 800−344−3860 Toll Free USA/Canada
Fax: 480−829−7709 or 800−344−3867 Toll Free USA/Canada
Email: orderlit@onsemi.com

N. American Technical Support: 800−282−9855 Toll Free
USA/Canada

ON Semiconductor Website: http://onsemi.com
Order Literature: http://www.onsemi.com/litorder

Japan: ON Semiconductor, Japan Customer Focus Center
2−9−1 Kamimeguro, Meguro−ku, Tokyo, Japan 153−0051
Phone: 81−3−5773−3850

http://onsemi.com
6

For additional information, please contact your
local Sales Representative.

MC74HC04A/D